forked from OSchip/llvm-project
92 lines
2.3 KiB
Plaintext
92 lines
2.3 KiB
Plaintext
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# RUN: llc -march=mipsel -mcpu=mips32r6 -start-after=block-placement %s -o - | FileCheck %s
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# Check that empty blocks in the cfg don't cause the mips hazard scheduler to
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# crash and that the nop is inserted correctly.
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# CHECK: blezc
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# CHECK: nop
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# CHECK: # BB#1:
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# CHECK: .insn
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# CHECK: # BB#2:
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# CHECK: .insn
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# CHECK: # BB#3:
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# CHECK: jal
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--- |
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; ModuleID = '<stdin>'
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source_filename = "<stdin>"
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target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
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declare i32 @k()
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declare void @f(i32)
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define void @l5() {
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entry:
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%call = tail call i32 @k()
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%cmp = icmp sgt i32 %call, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @f(i32 signext 2)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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---
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name: l5
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 24
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: true
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hasCalls: true
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maxCallFrameSize: 16
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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stack:
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- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%ra' }
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body: |
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bb.0.entry:
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successors: %bb.1.if.then(0x50000000), %bb.4.if.end(0x30000000)
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liveins: %ra
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%sp = ADDiu %sp, -24
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CFI_INSTRUCTION def_cfa_offset 24
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SW killed %ra, %sp, 20 :: (store 4 into %stack.0)
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CFI_INSTRUCTION offset %ra_64, -4
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JAL @k, csr_o32_fp64, implicit-def dead %ra, implicit-def %sp, implicit-def %v0
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BLEZ %v0, %bb.4.if.end, implicit-def %at
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bb.1.if.then:
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successors: %bb.2.if.then(0x80000000)
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bb.2.if.then:
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successors: %bb.3.if.then(0x80000000)
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bb.3.if.then:
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successors: %bb.4.if.end(0x80000000)
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%a0 = ADDiu %zero, 2
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JAL @f, csr_o32_fp64, implicit-def dead %ra, implicit killed %a0, implicit-def %sp
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bb.4.if.end:
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%ra = LW %sp, 20 :: (load 4 from %stack.0)
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%sp = ADDiu %sp, 24
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PseudoReturn undef %ra
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...
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