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llvm-project/llvm/test/CodeGen/Thumb2/thumb2-tbb.ll

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Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81293
2009-09-09 08:09:15 +08:00
; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s
Add Thumb2 pc relative add. llvm-svn: 74141
2009-06-25 07:47:58 +08:00
define void @bar(i32 %n.u) {
entry:
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; CHECK-LABEL: bar:
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
; CHECK: tbb
Refactor data-in-code annotations. Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
2012-05-19 03:12:01 +08:00
; CHECK: .data_region jt8
; CHECK: .end_data_region
; CHECK-NEXT: .align 1
Change Thumb2 jumptable codegen to one that uses two level jumps: Before: adr r12, #LJTI3_0_0 ldr pc, [r12, +r0, lsl #2] LJTI3_0_0: .long LBB3_24 .long LBB3_30 .long LBB3_31 .long LBB3_32 After: adr r12, #LJTI3_0_0 add pc, r12, +r0, lsl #2 LJTI3_0_0: b.w LBB3_24 b.w LBB3_30 b.w LBB3_31 b.w LBB3_32 This has several advantages. 1. This will make it easier to optimize this to a TBB / TBH instruction + (smaller) table. 2. This eliminate the need for ugly asm printer hack to force the address into thumb addresses (bit 0 is one). 3. Same codegen for pic and non-pic. 4. This eliminate the need to align the table so constantpool island pass won't have to over-estimate the size. Based on my calculation, the later is probably slightly faster as well since ldr pc with shifter address is very slow. That is, it should be a win as long as the HW implementation can do a reasonable job of branch predict the second branch. llvm-svn: 77024
2009-07-25 08:33:29 +08:00
Add Thumb2 pc relative add. llvm-svn: 74141
2009-06-25 07:47:58 +08:00
switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ]
bb:
tail call void(...)* @foo1()
ret void
bb1:
tail call void(...)* @foo2()
ret void
bb2:
tail call void(...)* @foo6()
ret void
bb3:
tail call void(...)* @foo3()
ret void
bb4:
tail call void(...)* @foo4()
ret void
bb5:
tail call void(...)* @foo5()
ret void
bb6:
tail call void(...)* @foo1()
ret void
bb7:
tail call void(...)* @foo2()
ret void
bb8:
tail call void(...)* @foo6()
ret void
bb9:
tail call void(...)* @foo3()
ret void
bb10:
tail call void(...)* @foo4()
ret void
bb11:
tail call void(...)* @foo5()
ret void
bb12:
tail call void(...)* @foo6()
ret void
}
declare void @foo1(...)
declare void @foo2(...)
declare void @foo6(...)
declare void @foo3(...)
declare void @foo4(...)
declare void @foo5(...)