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llvm-project/llvm/test/MC/Mips/set-mips-directives.s

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[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips1 | \
# RUN: FileCheck %s
.text
.set noreorder
.set mips1
add $2, $2, $2
.set mips2
ll $2,-2($2)
.set mips3
dadd $2,$2,$2
.set mips4
ldxc1 $f8,$2($4)
.set mips5
luxc1 $f19,$2($4)
.set mips32
clo $2,$2
.set mips32r2
rotr $2,15
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
.set mips32
.set mips32r3
rotr $2,15
.set mips32
.set mips32r5
rotr $2,15
[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
.set mips32r6
mod $2, $4, $6
.set mips64
daddi $2, $2, 10
.set mips64r2
drotr32 $1,$14,15
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
.set mips64
.set mips64r3
drotr32 $1,$14,15
.set mips64
.set mips64r5
drotr32 $1,$14,15
[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
.set mips64r6
mod $2, $4, $6
# CHECK: .set noreorder
# CHECK: .set mips1
# CHECK: add $2, $2, $2
# CHECK: .set mips2
# CHECK: ll $2, -2($2)
# CHECK: .set mips3
# CHECK: dadd $2, $2, $2
# CHECK: .set mips4
# CHECK: ldxc1 $f8, $2($4)
# CHECK: .set mips5
# CHECK: luxc1 $f19, $2($4)
# CHECK: .set mips32
# CHECK: clo $2, $2
# CHECK: .set mips32r2
# CHECK: rotr $2, $2, 15
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
# CHECK: .set mips32
# CHECK: .set mips32r3
# CHECK: rotr $2, $2, 15
# CHECK: .set mips32
# CHECK: .set mips32r5
# CHECK: rotr $2, $2, 15
[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
# CHECK: .set mips32r6
# CHECK: mod $2, $4, $6
# CHECK: .set mips64
# CHECK: daddi $2, $2, 10
# CHECK: .set mips64r2
# CHECK: drotr32 $1, $14, 15
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
# CHECK: .set mips64
# CHECK: .set mips64r3
# CHECK: drotr32 $1, $14, 15
# CHECK: .set mips64
# CHECK: .set mips64r5
# CHECK: drotr32 $1, $14, 15
[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
# CHECK: .set mips64r6
# CHECK: mod $2, $4, $6