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llvm-project/llvm/test/MC/Mips/micromips32r6/valid.s

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[mips][microMIPSr6] Implement BALC and BC instructions This patch implements BALC and BC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8388 llvm-svn: 235302
2015-04-20 21:04:14 +08:00
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
.set noat
[mips][microMIPSr6] Implement ADD, ADDU and ADDIU instructions Differential Revision: http://reviews.llvm.org/D8704 llvm-svn: 236111
2015-04-29 23:11:07 +08:00
add $3, $4, $5 # CHECK: add $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x10]
addiu $3, $4, 1234 # CHECK: addiu $3, $4, 1234 # encoding: [0x30,0x64,0x04,0xd2]
addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50]
[mips][microMIPSr6] Implement ADDIUPC and LWPC instructions This patch implements ADDIUPC and LWPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8415 llvm-svn: 236852
2015-05-08 21:52:04 +08:00
addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0x78,0x80,0x00,0x19]
[mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions Differential Revision: http://reviews.llvm.org/D10955 llvm-svn: 245554
2015-08-20 19:51:49 +08:00
addiur1sp $7, 4 # CHECK: addiur1sp $7, 4 # encoding: [0x6f,0x83]
addiur2 $6, $7, -1 # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
addiur2 $6, $7, 12 # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
addius5 $7, -2 # CHECK: addius5 $7, -2 # encoding: [0x4c,0xfc]
addiusp -1028 # CHECK: addiusp -1028 # encoding: [0x4f,0xff]
addiusp -1032 # CHECK: addiusp -1032 # encoding: [0x4f,0xfd]
addiusp 1024 # CHECK: addiusp 1024 # encoding: [0x4c,0x01]
addiusp 1028 # CHECK: addiusp 1028 # encoding: [0x4c,0x03]
addiusp -16 # CHECK: addiusp -16 # encoding: [0x4f,0xf9]
[mips][microMIPSr6] Implement ALUIPC and AUIPC instructions This patch implements ALUIPC and AUIPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8441 llvm-svn: 236858
2015-05-08 22:25:11 +08:00
aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0x78,0x7f,0x00,0x38]
[mips][microMIPSr6] Implement AND and ANDI instructions Differential Revision: http://reviews.llvm.org/D8772 llvm-svn: 237696
2015-05-19 21:32:31 +08:00
and $3, $4, $5 # CHECK: and $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x50]
andi $3, $4, 1234 # CHECK: andi $3, $4, 1234 # encoding: [0xd0,0x64,0x04,0xd2]
[mips][microMIPSr6] Implement ALUIPC and AUIPC instructions This patch implements ALUIPC and AUIPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8441 llvm-svn: 236858
2015-05-08 22:25:11 +08:00
auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0x78,0x7e,0xff,0xff]
[mips][microMIPSr6] Implement ALIGN and AUI instructions This patch implements ALIGN and AUI instructions using mapping. Differential Revision: http://reviews.llvm.org/D8782 llvm-svn: 237563
2015-05-18 19:44:30 +08:00
align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x00,0x43,0x24,0x1f]
aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x10,0x62,0xff,0xe9]
[mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions using mapping. Differential Revision: http://reviews.llvm.org/D10031 llvm-svn: 238325
2015-05-27 22:19:22 +08:00
beqzalc $2, 1332 # CHECK: beqzalc $2, 1332 # encoding: [0x74,0x40,0x02,0x9a]
bnezalc $2, 1332 # CHECK: bnezalc $2, 1332 # encoding: [0x7c,0x40,0x02,0x9a]
bgezalc $2, 1332 # CHECK: bgezalc $2, 1332 # encoding: [0xc0,0x42,0x02,0x9a]
bgtzalc $2, 1332 # CHECK: bgtzalc $2, 1332 # encoding: [0xe0,0x40,0x02,0x9a]
bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0xe0,0x42,0x02,0x9a]
blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0xc0,0x40,0x02,0x9a]
[mips][microMIPSr6] Implement BALC and BC instructions This patch implements BALC and BC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8388 llvm-svn: 235302
2015-04-20 21:04:14 +08:00
balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8]
bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8]
[mips][microMIPSr6] Implement BITSWAP instruction Implement BITSWAP instruction using mapping. Differential Revision: http://reviews.llvm.org/D8857 llvm-svn: 235321
2015-04-21 02:14:59 +08:00
bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c]
[mips][microMIPS] Implement BREAK, EHB and EI instructions http://reviews.llvm.org/D10090 llvm-svn: 240531
2015-06-24 18:32:16 +08:00
break # CHECK: break # encoding: [0x00,0x00,0x00,0x07]
break 7 # CHECK: break 7 # encoding: [0x00,0x07,0x00,0x07]
break 7, 5 # CHECK: break 7, 5 # encoding: [0x00,0x07,0x01,0x47]
[mips][microMIPSr6] Implement CACHE and PREF instructions Implement CACHE and PREF instructions using mapping. Differential Revision: http://reviews.llvm.org/D8893 llvm-svn: 235379
2015-04-21 19:17:25 +08:00
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08]
[mips][microMIPSr6] Implement CLO and CLZ instructions This patch implements CLO and CLZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8553 llvm-svn: 237257
2015-05-13 22:18:11 +08:00
clo $11, $a1 # CHECK: clo $11, $5 # encoding: [0x01,0x65,0x4b,0x3c]
clz $sp, $gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
[mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructions Differential Revision: http://reviews.llvm.org/D8769 llvm-svn: 237685
2015-05-19 19:21:37 +08:00
div $3, $4, $5 # CHECK: div $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x18]
divu $3, $4, $5 # CHECK: divu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x98]
[mips][microMIPS] Implement BREAK, EHB and EI instructions http://reviews.llvm.org/D10090 llvm-svn: 240531
2015-06-24 18:32:16 +08:00
ehb # CHECK: ehb # encoding: [0x00,0x00,0x18,0x00]
ei # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c]
ei $0 # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c]
ei $10 # CHECK: ei $10 # encoding: [0x00,0x0a,0x57,0x7c]
[mips][microMIPS] Implement ERET and ERETNC instructions http://reviews.llvm.org/D10091 llvm-svn: 239522
2015-06-11 18:22:46 +08:00
eret # CHECK: eret # encoding: [0x00,0x00,0xf3,0x7c]
eretnc # CHECK: eretnc # encoding: [0x00,0x01,0xf3,0x7c]
[mips][microMIPSr6] Implement JIALC and JIC instructions This patch implements JIALC and JIC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8389 llvm-svn: 236748
2015-05-08 01:12:23 +08:00
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00]
[mips][microMIPSr6] Implement LSA instruction This patch implements LSA instruction using mapping. Differential Revision: http://reviews.llvm.org/D8919 llvm-svn: 237634
2015-05-19 07:12:10 +08:00
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x26,0x0f]
[mips][microMIPSr6] Implement ADDIUPC and LWPC instructions This patch implements ADDIUPC and LWPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8415 llvm-svn: 236852
2015-05-08 21:52:04 +08:00
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
[mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructions Differential Revision: http://reviews.llvm.org/D8769 llvm-svn: 237685
2015-05-19 19:21:37 +08:00
mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58]
modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8]
[mips][microMIPSr6] Implement MUL, MUH, MULU and MUHU instructions Differential Revision: http://reviews.llvm.org/D8894 llvm-svn: 236131
2015-04-30 01:23:22 +08:00
mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]
muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]
mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]
muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]
[mips][microMIPS] Implement SLL and NOP instructions http://reviews.llvm.org/D10474 llvm-svn: 241150
2015-07-01 17:54:51 +08:00
nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
[mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions Differential Revision: http://reviews.llvm.org/D8800 llvm-svn: 237697
2015-05-19 22:12:55 +08:00
nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0]
or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90]
ori $3, $4, 1234 # CHECK: ori $3, $4, 1234 # encoding: [0x50,0x64,0x04,0xd2]
[mips][microMIPSr6] Implement CACHE and PREF instructions Implement CACHE and PREF instructions using mapping. Differential Revision: http://reviews.llvm.org/D8893 llvm-svn: 235379
2015-04-21 19:17:25 +08:00
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08]
[mips][microMIPSr6] Implement SEB and SEH instructions Differential Revision: http://reviews.llvm.org/D9739 llvm-svn: 238333
2015-05-27 23:39:47 +08:00
seb $3, $4 # CHECK: seb $3, $4 # encoding: [0x00,0x64,0x2b,0x3c]
seh $3, $4 # CHECK: seh $3, $4 # encoding: [0x00,0x64,0x3b,0x3c]
[mips][microMIPSr6] Implement SELEQZ and SELNEZ instructions This patch implements SELEQZ and SELNEZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8497 llvm-svn: 237158
2015-05-13 01:39:32 +08:00
seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x83,0x11,0x40]
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x83,0x11,0x80]
[mips][microMIPS] Implement SLL and NOP instructions http://reviews.llvm.org/D10474 llvm-svn: 241150
2015-07-01 17:54:51 +08:00
sll $4, $3, 7 # CHECK: sll $4, $3, 7 # encoding: [0x00,0x83,0x38,0x00]
[mips][microMIPSr6] Implement SUB and SUBU instructions Differential Revision: http://reviews.llvm.org/D8764 llvm-svn: 236118
2015-04-30 00:22:46 +08:00
sub $3, $4, $5 # CHECK: sub $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x90]
subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0]
[mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions Differential Revision: http://reviews.llvm.org/D8800 llvm-svn: 237697
2015-05-19 22:12:55 +08:00
xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
[mips][microMIPS] Implement SW and SWE instructions Differential Revision: http://reviews.llvm.org/D10869 llvm-svn: 245293
2015-08-18 20:53:08 +08:00
sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]
swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
[mips][microMIPSr6] Implement SUB and SUBU instructions Differential Revision: http://reviews.llvm.org/D8764 llvm-svn: 236118
2015-04-30 00:22:46 +08:00