2011-04-16 05:51:11 +08:00
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//===- MipsSubtarget.cpp - Mips Subtarget Information -----------*- C++ -*-===//
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2007-06-06 15:42:06 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 15:42:06 +08:00
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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//
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2011-07-02 05:01:15 +08:00
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// This file implements the Mips specific subclass of TargetSubtargetInfo.
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2007-06-06 15:42:06 +08:00
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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#include "MipsSubtarget.h"
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#include "Mips.h"
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2011-07-02 04:45:01 +08:00
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_MC_DESC
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#define GET_SUBTARGETINFO_TARGET_DESC
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2011-07-02 06:36:09 +08:00
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#include "MipsGenSubtargetInfo.inc"
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using namespace llvm;
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2011-06-30 09:53:36 +08:00
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MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, bool little) :
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2011-07-07 15:07:08 +08:00
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MipsGenSubtargetInfo(TT, CPU, FS),
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
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2009-08-03 10:22:28 +08:00
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IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true),
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HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false),
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HasSwap(false), HasBitCount(false)
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{
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2011-06-30 09:53:36 +08:00
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "mips1";
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2009-05-28 01:23:44 +08:00
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MipsArchVersion = Mips1;
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2007-06-06 15:42:06 +08:00
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// Parse features string.
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2011-07-07 15:07:08 +08:00
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ParseSubtargetFeatures(CPUName, FS);
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2008-07-14 22:42:54 +08:00
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2011-07-02 04:45:01 +08:00
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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2008-07-14 22:42:54 +08:00
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// Is the target system Linux ?
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if (TT.find("linux") == std::string::npos)
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IsLinux = false;
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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2011-03-05 01:51:39 +08:00
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// When only the target triple is specified and is
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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// a allegrex target, set the features. We also match
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// big and little endian allegrex cores (dont really
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// know if a big one exists)
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2008-08-08 12:49:42 +08:00
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if (TT.find("mipsallegrex") != std::string::npos ||
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TT.find("psp") != std::string::npos) {
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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MipsABI = EABI;
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IsSingleFloat = true;
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MipsArchVersion = Mips2;
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2008-07-09 13:32:22 +08:00
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HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
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HasSEInReg = true;
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2008-08-08 14:16:31 +08:00
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HasBitCount = true;
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2008-08-13 15:13:40 +08:00
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HasSwap = true;
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HasCondMov = true;
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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}
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2007-06-06 15:42:06 +08:00
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}
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