llvm-project/llvm/test/CodeGen/RISCV/lit.local.cfg

if not 'RISCV' in config.root.targets:
    config.unsupported = True
[RISCV] Initial codegen support for ALU operations This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188 2017-10-20 05:37:38 +08:00			`if not 'RISCV' in config.root.targets:`
			`config.unsupported = True`