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llvm-project/llvm/test/CodeGen/SystemZ/setcc-01.ll

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[SystemZ] Automatically detect zEC12 and z196 hosts As on other hosts, the CPU identification instruction is priveleged, so we need to look through /proc/cpuinfo. I copied the PowerPC way of handling "generic". Several tests were implicitly assuming z10 and so failed on z196. llvm-svn: 193742
2013-10-31 20:14:17 +08:00
; Test SETCC for every integer condition. The tests here assume that
; RISBLG isn't available.
[SystemZ] Improve handling of SETCC We previously used the default expansion to SELECT_CC, which in turn would expand to "LHI; BRC; LHI". In most cases it's better to use an IPM-based sequence instead. llvm-svn: 192784
2013-10-16 19:10:55 +08:00
;
[SystemZ] Automatically detect zEC12 and z196 hosts As on other hosts, the CPU identification instruction is priveleged, so we need to look through /proc/cpuinfo. I copied the PowerPC way of handling "generic". Several tests were implicitly assuming z10 and so failed on z196. llvm-svn: 193742
2013-10-31 20:14:17 +08:00
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
[SystemZ] Improve handling of SETCC We previously used the default expansion to SELECT_CC, which in turn would expand to "LHI; BRC; LHI". In most cases it's better to use an IPM-based sequence instead. llvm-svn: 192784
2013-10-16 19:10:55 +08:00
; Test CC in { 0 }, with 3 don't care.
define i32 @f1(i32 %a, i32 %b) {
; CHECK-LABEL: f1:
; CHECK: ipm %r2
; CHECK-NEXT: afi %r2, -268435456
; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14
%cond = icmp eq i32 %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 1 }, with 3 don't care.
define i32 @f2(i32 %a, i32 %b) {
; CHECK-LABEL: f2:
; CHECK: ipm [[REG:%r[0-5]]]
; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36
; CHECK: br %r14
%cond = icmp slt i32 %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 0, 1 }, with 3 don't care.
define i32 @f3(i32 %a, i32 %b) {
; CHECK-LABEL: f3:
; CHECK: ipm %r2
; CHECK-NEXT: afi %r2, -536870912
; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14
%cond = icmp sle i32 %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 2 }, with 3 don't care.
define i32 @f4(i32 %a, i32 %b) {
; CHECK-LABEL: f4:
; CHECK: ipm [[REG:%r[0-5]]]
; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35
; CHECK: br %r14
%cond = icmp sgt i32 %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 0, 2 }, with 3 don't care.
define i32 @f5(i32 %a, i32 %b) {
; CHECK-LABEL: f5:
; CHECK: ipm [[REG:%r[0-5]]]
; CHECK-NEXT: xilf [[REG]], 4294967295
; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36
; CHECK: br %r14
%cond = icmp sge i32 %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 1, 2 }, with 3 don't care.
define i32 @f6(i32 %a, i32 %b) {
; CHECK-LABEL: f6:
; CHECK: ipm %r2
; CHECK-NEXT: afi %r2, 1879048192
; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14
%cond = icmp ne i32 %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}