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llvm-project/llvm/test/CodeGen/RISCV/double-previous-failure.ll

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[RISCV] Codegen support for RV32D floating point comparison operations Also add double-prevoius-failure.ll which captures a test case that at one point triggered a compiler crash, while developing calling convention support for f64 on RV32D with soft-float ABI. llvm-svn: 329877
2018-04-12 13:50:06 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
define double @test(double %a) nounwind {
; RV32IFD-LABEL: test:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: ret
ret double %a
}
; This previously failed complaining of multiple vreg defs due to an ABI
; lowering issue.
define i32 @main() nounwind {
; RV32IFD-LABEL: main:
; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
Revert Patch from Phabricator This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
2019-09-17 18:52:09 +08:00
; RV32IFD-NEXT: lui a1, 262144
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32IFD-NEXT: mv a0, zero
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32IFD-NEXT: call test
[RISCV] Codegen support for RV32D floating point comparison operations Also add double-prevoius-failure.ll which captures a test case that at one point triggered a compiler crash, while developing calling convention support for f64 on RV32D with soft-float ABI. llvm-svn: 329877
2018-04-12 13:50:06 +08:00
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp)
[RISCV] Add DAGCombine for (SplitF64 (ConstantFP x)) The SplitF64 node is used on RV32D to convert an f64 directly to a pair of i32 (necessary as bitcasting to i64 isn't legal). When performed on a ConstantFP, this will result in a FP load from the constant pool followed by a store to the stack and two integer loads from the stack (necessary as there is no way to directly move between f64 FPRs and i32 GPRs on RV32D). It's always cheaper to just materialise integers for the lo and hi parts of the FP constant, so do that instead. llvm-svn: 357341
2019-03-30 17:15:47 +08:00
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
[RISCV] Support Constant Pools in Load/Store Peephole Summary: RISC-V uses a post-select peephole pass to optimise `(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`. This peephole wasn't firing for accesses to constant pools, which is how we materialise most floating point constants. This adds support for the constantpool case, which improves code generation for lots of small FP loading examples. I have not added any tests because this structure is well-covered by the `fp-imm.ll` testcases, as well as almost all other uses of floating point constants in the RISC-V backend tests. Reviewed By: luismarques, asb Differential Revision: https://reviews.llvm.org/D79523
2020-05-12 01:52:42 +08:00
; RV32IFD-NEXT: fld ft1, %lo(.LCPI1_0)(a0)
[RISCV] Add DAGCombine for (SplitF64 (ConstantFP x)) The SplitF64 node is used on RV32D to convert an f64 directly to a pair of i32 (necessary as bitcasting to i64 isn't legal). When performed on a ConstantFP, this will result in a FP load from the constant pool followed by a store to the stack and two integer loads from the stack (necessary as there is no way to directly move between f64 FPRs and i32 GPRs on RV32D). It's always cheaper to just materialise integers for the lo and hi parts of the FP constant, so do that instead. llvm-svn: 357341
2019-03-30 17:15:47 +08:00
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV32IFD-NEXT: fld ft2, %lo(.LCPI1_1)(a0)
; RV32IFD-NEXT: flt.d a0, ft0, ft1
; RV32IFD-NEXT: not a0, a0
; RV32IFD-NEXT: flt.d a1, ft2, ft0
; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: and a0, a0, a1
; RV32IFD-NEXT: bnez a0, .LBB1_2
; RV32IFD-NEXT: # %bb.1: # %if.then
; RV32IFD-NEXT: call abort
; RV32IFD-NEXT: .LBB1_2: # %if.end
[RISCV] Codegen support for RV32D floating point comparison operations Also add double-prevoius-failure.ll which captures a test case that at one point triggered a compiler crash, while developing calling convention support for f64 on RV32D with soft-float ABI. llvm-svn: 329877
2018-04-12 13:50:06 +08:00
; RV32IFD-NEXT: mv a0, zero
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32IFD-NEXT: call exit
[RISCV] Codegen support for RV32D floating point comparison operations Also add double-prevoius-failure.ll which captures a test case that at one point triggered a compiler crash, while developing calling convention support for f64 on RV32D with soft-float ABI. llvm-svn: 329877
2018-04-12 13:50:06 +08:00
entry:
%call = call double @test(double 2.000000e+00)
%cmp = fcmp olt double %call, 2.400000e-01
%cmp2 = fcmp ogt double %call, 2.600000e-01
%or.cond = or i1 %cmp, %cmp2
br i1 %or.cond, label %if.then, label %if.end
if.then:
call void @abort()
unreachable
if.end:
call void @exit(i32 0)
unreachable
}
declare void @abort()
declare void @exit(i32)