forked from OSchip/llvm-project
112 lines
3.9 KiB
Plaintext
112 lines
3.9 KiB
Plaintext
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# RUN: llc -o - %s -mtriple aarch64-unknown -mattr=fuse-arith-logic -run-pass=machine-scheduler -misched-print-dags |& FileCheck %s
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# REQUIRES: asserts
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---
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name: arith
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body: |
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bb.0.entry:
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%0:gpr32 = SUBWrr undef $w0, undef $w1
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%1:gpr32 = ADDWrr undef $w1, undef $w2
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%2:gpr32 = SUBWrs %0, undef $w2, 0
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%3:gpr32 = ADDWrs %1, undef $w3, 0
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; CHECK: SU(0): %0:gpr32 = SUBWrr undef $w0, undef $w1
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; CHECK: Successors:
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; CHECK: SU(2): Ord Latency=0 Cluster
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; CHECK: SU(1): %1:gpr32 = ADDWrr undef $w1, undef $w2
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; CHECK: Successors:
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; CHECK: SU(3): Ord Latency=0 Cluster
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; CHECK: SU(2): dead %2:gpr32 = SUBWrs %0:gpr32, undef $w2, 0
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; CHECK: Predecessors:
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; CHECK: SU(0): Ord Latency=0 Cluster
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; CHECK: SU(3): dead %3:gpr32 = ADDWrs %1:gpr32, undef $w3, 0
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; CHECK: Predecessors:
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; CHECK: SU(1): Ord Latency=0 Cluster
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...
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---
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name: compare
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body: |
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bb.0.entry:
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%0:gpr64 = ADDXrr undef $x0, undef $x1
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%1:gpr64 = SUBXrs undef $x1, undef $x2, 0
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%2:gpr64 = ADDSXrr %0, undef $x3, implicit-def $nzcv
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%3:gpr64 = SUBSXrs %1, undef $x4, 0, implicit-def $nzcv
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; CHECK: SU(0): %0:gpr64 = ADDXrr undef $x0, undef $x1
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; CHECK: Successors:
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; CHECK: SU(2): Ord Latency=0 Cluster
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; CHECK: SU(1): %1:gpr64 = SUBXrs undef $x1, undef $x2, 0
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; CHECK: Successors:
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; CHECK: SU(3): Ord Latency=0 Cluster
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; CHECK: SU(2): dead %2:gpr64 = ADDSXrr %0:gpr64, undef $x3, implicit-def $nzcv
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; CHECK: Predecessors:
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; CHECK: SU(0): Ord Latency=0 Cluster
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; CHECK: SU(3): dead %3:gpr64 = SUBSXrs %1:gpr64, undef $x4, 0, implicit-def $nzcv
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; CHECK: Predecessors:
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; CHECK: SU(1): Ord Latency=0 Cluster
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...
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---
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name: logic
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body: |
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bb.0.entry:
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%0:gpr32 = ADDWrr undef $w0, undef $w1
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%1:gpr64 = SUBXrs undef $x1, undef $x2, 0
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%3:gpr32 = ANDWrs %0, undef $w3, 0
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%4:gpr64 = ORRXrr %1, undef $x4
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; CHECK: SU(0): %0:gpr32 = ADDWrr undef $w0, undef $w1
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; CHECK: Successors:
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; CHECK: SU(2): Ord Latency=0 Cluster
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; CHECK: SU(1): %1:gpr64 = SUBXrs undef $x1, undef $x2, 0
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; CHECK: Successors:
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; CHECK: SU(3): Ord Latency=0 Cluster
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; CHECK: SU(2): dead %2:gpr32 = ANDWrs %0:gpr32, undef $w3, 0
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; CHECK: Predecessors:
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; CHECK: SU(0): Ord Latency=0 Cluster
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; CHECK: SU(3): dead %3:gpr64 = ORRXrr %1:gpr64, undef $x4
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; CHECK: Predecessors:
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; CHECK: SU(1): Ord Latency=0 Cluster
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...
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---
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name: nope
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body: |
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bb.0.entry:
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; Shifted register.
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%0:gpr32 = SUBWrr undef $w0, undef $w1
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%1:gpr32 = SUBWrs %0, undef $w2, 1
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; CHECKSU(0)%0:gpr32 = SUBWrr undef $w0, undef $w1
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; CHECKSuccessors:
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; CHECK-NOTSU(1)Ord Latency=0 Cluster
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; CHECKSU(1)dead %1:gpr32 = SUBWrs %0:gpr32, undef $w2, 1
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; Multiple successors.
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%2:gpr64 = ADDXrr undef $x0, undef $x1
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%3:gpr32 = EXTRACT_SUBREG %2, %subreg.sub_32
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%4:gpr32 = ANDWrs %3, undef $w2, 0
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%5:gpr64 = ADDSXrr %2, undef $x3, implicit-def $nzcv
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; CHECKSU(2)%2:gpr64 = ADDXrr undef $x0, undef $x1
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; CHECKSuccessors:
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; CHECK-NOTSU(3)Ord Latency=0 Cluster
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; CHECKSU(5)Ord Latency=0 Cluster
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; CHECKSU(3)%3:gpr32 = EXTRACT_SUBREG %2:gpr64, %subreg.sub_32
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; CHECKSU(5)dead %5:gpr64 = ADDSXrr %2:gpr64, undef $x3, implicit-def $nzcv
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; Different register sizes.
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%6:gpr32 = SUBWrr undef $w0, undef $w1
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%7:gpr64 = ADDXrr undef $x1, undef $x2
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%8:gpr64 = SUBXrr %7, undef $x3
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%9:gpr32 = ADDWrr %6, undef $w4
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; CHECKSU(6)%6:gpr32 = SUBWrr undef $w0, undef $w1
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; CHECKSuccessors:
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; CHECK-NOTSU(8)Ord Latency=0 Cluster
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; CHECKSU(7)%7:gpr64 = ADDXrr undef $x1, undef $x2
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; CHECKSuccessors:
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; CHECK-NOTSU(9)Ord Latency=0 Cluster
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; CHECKSU(8)dead %8:gpr64 = SUBXrr %7:gpr64, undef $x3
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; CHECKPredecessors:
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; CHECKSU(7)Ord Latency=0 Cluster
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; CHECKSU(9)dead %9:gpr32 = ADDWrr %6:gpr32, undef $w4
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; CHECKPredecessors:
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; CHECKSU(6)Ord Latency=0 Cluster
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...
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