2020-05-28 18:29:26 +08:00
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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2020-07-09 17:16:32 +08:00
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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2020-05-28 18:29:26 +08:00
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; WARN-NOT: warning
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[Aarch64][SVE] Add intrinsics for scatter stores
Summary:
This patch adds the following SVE intrinsics for scatter stores:
* 64-bit offsets:
* @llvm.aarch64.sve.st1.scatter (unscaled)
* @llvm.aarch64.sve.st1.scatter.index (scaled)
* 32-bit unscaled offsets:
* @llvm.aarch64.sve.st1.scatter.uxtw (zero-extended offset)
* @llvm.aarch64.sve.st1.scatter.sxtw (sign-extended-offset)
* 32-bit scaled offsets:
* @llvm.aarch64.sve.st1.scatter.uxtw.index (zero-extended offset)
* @llvm.aarch64.sve.st1.scatter.sxtw.index (sign-extended offset)
* vector base + immediate:
* @llvm.aarch64.sve.st1.scatter.imm
Reviewers: rengolin, efriedma, sdesmalen
Reviewed By: efriedma, sdesmalen
Subscribers: kmclaughlin, eli.friedman, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71074
2019-12-16 19:51:10 +08:00
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;
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; ST1H, ST1W, ST1D: base + 64-bit scaled offset
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; e.g. st1h { z0.d }, p0, [x0, z0.d, lsl #1]
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;
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define void @sst1h_index(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i64> %offsets) {
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; CHECK-LABEL: sst1h_index
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; CHECK: st1h { z0.d }, p0, [x0, z1.d, lsl #1]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
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call void @llvm.aarch64.sve.st1.scatter.index.nxv2i16(<vscale x 2 x i16> %data_trunc,
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<vscale x 2 x i1> %pg,
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i16* %base,
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<vscale x 2 x i64> %offsets)
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ret void
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}
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define void @sst1w_index(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i64> %offsets) {
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; CHECK-LABEL: sst1w_index
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; CHECK: st1w { z0.d }, p0, [x0, z1.d, lsl #2]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
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call void @llvm.aarch64.sve.st1.scatter.index.nxv2i32(<vscale x 2 x i32> %data_trunc,
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<vscale x 2 x i1> %pg,
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i32* %base,
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<vscale x 2 x i64> %offsets)
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ret void
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}
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define void @sst1d_index(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i64* %base, <vscale x 2 x i64> %offsets) {
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; CHECK-LABEL: sst1d_index
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; CHECK: st1d { z0.d }, p0, [x0, z1.d, lsl #3]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.index.nxv2i64(<vscale x 2 x i64> %data,
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<vscale x 2 x i1> %pg,
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i64* %base,
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<vscale x 2 x i64> %offsets)
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ret void
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}
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define void @sst1d_index_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, double* %base, <vscale x 2 x i64> %offsets) {
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; CHECK-LABEL: sst1d_index_double
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; CHECK: st1d { z0.d }, p0, [x0, z1.d, lsl #3]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.index.nxv2f64(<vscale x 2 x double> %data,
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<vscale x 2 x i1> %pg,
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double* %base,
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<vscale x 2 x i64> %offsets)
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ret void
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}
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declare void @llvm.aarch64.sve.st1.scatter.index.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i16*, <vscale x 2 x i64>)
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declare void @llvm.aarch64.sve.st1.scatter.index.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32*, <vscale x 2 x i64>)
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declare void @llvm.aarch64.sve.st1.scatter.index.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*, <vscale x 2 x i64>)
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declare void @llvm.aarch64.sve.st1.scatter.index.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*, <vscale x 2 x i64>)
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