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llvm-project/llvm/test/CodeGen/WebAssembly/load-ext.ll

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WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
; RUN: llc < %s -asm-verbose=false | FileCheck %s
; Test that extending loads are assembled properly.
[WebAssembly] Add -m:e to the target triple. This enables ELF-style name mangling, which primarily means using ".L" for private symbols. llvm-svn: 257020
2016-01-07 11:19:23 +08:00
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
target triple = "wasm32-unknown-unknown"
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: sext_i8_i32:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
; CHECK: i32.load8_s $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-26 00:55:01 +08:00
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
define i32 @sext_i8_i32(i8 *%p) {
%v = load i8, i8* %p
%e = sext i8 %v to i32
ret i32 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: zext_i8_i32:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
; CHECK: i32.load8_u $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-26 00:55:01 +08:00
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
define i32 @zext_i8_i32(i8 *%p) {
%v = load i8, i8* %p
%e = zext i8 %v to i32
ret i32 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: sext_i16_i32:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
; CHECK: i32.load16_s $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-26 00:55:01 +08:00
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
define i32 @sext_i16_i32(i16 *%p) {
%v = load i16, i16* %p
%e = sext i16 %v to i32
ret i32 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: zext_i16_i32:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
; CHECK: i32.load16_u $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-26 00:55:01 +08:00
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
define i32 @zext_i16_i32(i16 *%p) {
%v = load i16, i16* %p
%e = zext i16 %v to i32
ret i32 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: sext_i8_i64:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
; CHECK: i64.load8_s $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-26 00:55:01 +08:00
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
define i64 @sext_i8_i64(i8 *%p) {
%v = load i8, i8* %p
%e = sext i8 %v to i64
ret i64 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: zext_i8_i64:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
; CHECK: i64.load8_u $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-26 00:55:01 +08:00
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
define i64 @zext_i8_i64(i8 *%p) {
%v = load i8, i8* %p
%e = zext i8 %v to i64
ret i64 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: sext_i16_i64:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
; CHECK: i64.load16_s $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-26 00:55:01 +08:00
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
define i64 @sext_i16_i64(i16 *%p) {
%v = load i16, i16* %p
%e = sext i16 %v to i64
ret i64 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: zext_i16_i64:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
; CHECK: i64.load16_u $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-26 00:55:01 +08:00
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
define i64 @zext_i16_i64(i16 *%p) {
%v = load i16, i16* %p
%e = zext i16 %v to i64
ret i64 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: sext_i32_i64:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
; CHECK: i64.load32_s $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-26 00:55:01 +08:00
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
define i64 @sext_i32_i64(i32 *%p) {
%v = load i32, i32* %p
%e = sext i32 %v to i64
ret i64 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: zext_i32_i64:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
; CHECK: i64.load32_u $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-26 00:55:01 +08:00
; CHECK: return $pop0{{$}}
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
define i64 @zext_i32_i64(i32 *%p) {
%v = load i32, i32* %p
%e = zext i32 %v to i64
ret i64 %e
}