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llvm-project/llvm/test/CodeGen/X86/fast-isel-sse12-fptoint.ll

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Change the fast-isel-abort option from bool to int to enable "levels" Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 230775
2015-02-28 02:32:11 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=AVX
[FastISel][X86] Add support for cvttss2si/cvttsd2si intrinsics. This adds support for the cvttss2si/cvttsd2si intrinsics. Preceding insertelement instructions are folded into the conversion instruction (if possible). llvm-svn: 210870
2014-06-13 10:21:58 +08:00
define i32 @cvt_test1(float %a) {
; SSE-LABEL: cvt_test1
; SSE: cvttss2si %xmm0, %eax
; AVX-LABEL: cvt_test1
; AVX: vcvttss2si %xmm0, %eax
%1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 0.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 0.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 0.000000e+00, i32 3
%5 = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %4)
ret i32 %5
}
declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone
define i64 @cvt_test2(float %a) {
; SSE-LABEL: cvt_test2
; SSE: cvttss2si %xmm0, %rax
; AVX-LABEL: cvt_test2
; AVX: vcvttss2si %xmm0, %rax
%1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 0.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 0.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 0.000000e+00, i32 3
%5 = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %4)
ret i64 %5
}
declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone
define i32 @cvt_test3(double %a) {
; SSE-LABEL: cvt_test3
; SSE: cvttsd2si %xmm0, %eax
; AVX-LABEL: cvt_test3
; AVX: vcvttsd2si %xmm0, %eax
%1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 0.000000e+00, i32 1
%3 = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %2)
ret i32 %3
}
declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone
define i64 @cvt_test4(double %a) {
; SSE-LABEL: cvt_test4
; SSE: cvttsd2si %xmm0, %rax
; AVX-LABEL: cvt_test4
; AVX: vcvttsd2si %xmm0, %rax
%1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 0.000000e+00, i32 1
%3 = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %2)
ret i64 %3
}
declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone