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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir

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Canonicalize a large number of mir tests using update_mir_test_checks This converts a large and somewhat arbitrary set of tests to use update_mir_test_checks. I ran the script on all of the tests I expect to need to modify for an upcoming mir syntax change and kept the ones that obviously didn't change the tests in ways that might make it harder to understand. llvm-svn: 316137
2017-10-19 07:18:12 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
AMDGPU/GlobalISel: Legalize select for v4s16 Also add some more select tests to help show future legalization changes. llvm-svn: 353045
2019-02-04 22:04:52 +08:00
# RUN: llc -O0 -march=amdgcn -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
AMDGPU/GlobalISel: Mark 32-bit G_SELECT as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33949 llvm-svn: 304910
2017-06-07 21:54:51 +08:00
---
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
name: test_select_s32
AMDGPU/GlobalISel: Mark 32-bit G_SELECT as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33949 llvm-svn: 304910
2017-06-07 21:54:51 +08:00
body: |
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $vgpr0
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK-LABEL: name: test_select_s32
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK: $vgpr0 = COPY [[SELECT]](s32)
AMDGPU/GlobalISel: Test cleanups Remove IR and registers sections llvm-svn: 349011
2018-12-13 16:11:45 +08:00
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
AMDGPU/GlobalISel: Mark 32-bit G_SELECT as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33949 llvm-svn: 304910
2017-06-07 21:54:51 +08:00
AMDGPU/GlobalISel: Test cleanups Remove IR and registers sections llvm-svn: 349011
2018-12-13 16:11:45 +08:00
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s32) = G_CONSTANT i32 1
%4:_(s32) = G_CONSTANT i32 2
%5:_(s32) = G_SELECT %2, %3, %4
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
$vgpr0 = COPY %5
AMDGPU/GlobalISel: Mark 32-bit G_SELECT as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33949 llvm-svn: 304910
2017-06-07 21:54:51 +08:00
...
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
---
name: test_select_s64
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_select_s64
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s64) = G_CONSTANT i64 1
%4:_(s64) = G_CONSTANT i64 2
%5:_(s64) = G_SELECT %2, %3, %4
$vgpr0_vgpr1 = COPY %5
...
AMDGPU/GlobalISel: Fix non-power-of-2 select llvm-svn: 357762
2019-04-05 22:03:04 +08:00
---
name: test_select_s48
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_select_s48
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[SELECT]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY3]](s64)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s48) = G_CONSTANT i48 1
%4:_(s48) = G_CONSTANT i48 2
%5:_(s48) = G_SELECT %2, %3, %4
%6:_(s64) = G_ANYEXT %5
$vgpr0_vgpr1 = COPY %6
...
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
---
name: test_select_s16
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_select_s16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
AMDGPU/GlobalISel: Make 16-bit constants legal This is mostly for the benefit of patterns which use 16-bit constants. llvm-svn: 370921
2019-09-05 00:19:45 +08:00
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
AMDGPU/GlobalISel: Make s16 select legal This is easy to handle and avoids legalization artifacts which are likely to obscure combines. llvm-svn: 364787
2019-07-01 23:42:47 +08:00
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s16) = G_CONSTANT i16 1
%4:_(s16) = G_CONSTANT i16 2
%5:_(s16) = G_SELECT %2, %3, %4
%6:_(s32) = G_ANYEXT %5
$vgpr0 = COPY %6
...
---
name: test_select_s8
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_select_s8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
[GlobalISel][AArch64][AMDGPU][X86] Teach LegalizationArtifactCombiner to combine trunc(g_constant). This allows X86 to properly form shift by immediate instructions since we require an 8-bit constant to match the imported SelectionDAG patterns.
2019-10-25 03:08:02 +08:00
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
AMDGPU/GlobalISel: Make s16 select legal This is easy to handle and avoids legalization artifacts which are likely to obscure combines. llvm-svn: 364787
2019-07-01 23:42:47 +08:00
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(s1) = G_ICMP intpred(ne), %0, %1
GlobalISel: Enforce operand types for constants A number of of tests were using imm operands, not cimm. Since CSE relies on the exact ConstantInt* pointer used, and implicit conversions are generally evil, also enforce the bitsize of the types. llvm-svn: 353113
2019-02-05 07:29:31 +08:00
%3:_(s8) = G_CONSTANT i8 1
%4:_(s8) = G_CONSTANT i8 2
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%5:_(s8) = G_SELECT %2, %3, %4
%6:_(s32) = G_ANYEXT %5
$vgpr0 = COPY %6
...
---
name: test_select_s7
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_select_s7
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
[GlobalISel][AArch64][AMDGPU][X86] Teach LegalizationArtifactCombiner to combine trunc(g_constant). This allows X86 to properly form shift by immediate instructions since we require an 8-bit constant to match the imported SelectionDAG patterns.
2019-10-25 03:08:02 +08:00
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
AMDGPU/GlobalISel: Make s16 select legal This is easy to handle and avoids legalization artifacts which are likely to obscure combines. llvm-svn: 364787
2019-07-01 23:42:47 +08:00
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(s1) = G_ICMP intpred(ne), %0, %1
GlobalISel: Enforce operand types for constants A number of of tests were using imm operands, not cimm. Since CSE relies on the exact ConstantInt* pointer used, and implicit conversions are generally evil, also enforce the bitsize of the types. llvm-svn: 353113
2019-02-05 07:29:31 +08:00
%3:_(s7) = G_CONSTANT i7 1
%4:_(s7) = G_CONSTANT i7 2
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%5:_(s7) = G_SELECT %2, %3, %4
%6:_(s32) = G_ANYEXT %5
$vgpr0 = COPY %6
...
GlobalISel: Implement narrowScalar for select Don't handle vector conditions. I think this can be merged in the future with fewerElementsVectorSelect, although this becomes slightly tricky with a vector condition. llvm-svn: 353122
2019-02-05 08:13:44 +08:00
---
name: test_select_s96
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5 , $vgpr6
; CHECK-LABEL: name: test_select_s96
; CHECK: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr6
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[C]]
; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s96), 0
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s96), 64
; CHECK: [[EXTRACT2:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s96), 0
; CHECK: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s96), 64
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[EXTRACT]], [[EXTRACT2]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[EXTRACT1]], [[EXTRACT3]]
; CHECK: [[DEF:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF
; CHECK: [[INSERT:%[0-9]+]]:_(s96) = G_INSERT [[DEF]], [[SELECT]](s64), 0
; CHECK: [[INSERT1:%[0-9]+]]:_(s96) = G_INSERT [[INSERT]], [[SELECT1]](s32), 64
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT1]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s32) = COPY $vgpr6
%3:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(ne), %2, %3
%5:_(s96) = G_SELECT %4, %0, %1
$vgpr0_vgpr1_vgpr2 = COPY %5
...
---
name: test_select_s128
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7 , $vgpr8
; CHECK-LABEL: name: test_select_s128
; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[C]]
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT1]](s64)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s128) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
%2:_(s32) = COPY $vgpr8
%3:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(ne), %2, %3
%5:_(s128) = G_SELECT %4, %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5
...
AMDGPU/GlobalISel: Legalize select for v4s16 Also add some more select tests to help show future legalization changes. llvm-svn: 353045
2019-02-04 22:04:52 +08:00
---
name: test_select_v2s8
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
; CHECK-LABEL: name: test_select_v2s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr3_vgpr4
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC G_BITCAST can be lowered with a pair of G_UNMERGE_VALUES and G_MERGE_VALUES with different types, but G_UNMERGE_VALUES of a vector can also be implemented with a bitcast to a scalar, which introduces the possibility for infinite loops. Try to eliminate an illegal source register type in the artifact combiner to avoid this from happening. Avoids infinite looping in the legalizer in a future patch which allows lowering G_UNMERGE_VALUES of a vector source with a G_BITCAST.
2020-04-05 03:07:28 +08:00
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC2]], [[TRUNC3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
[GlobalISel] Legalizer: Retry combining illegal artifacts as long as there new artifacts Summary: Currently, Legalizer aborts if it’s unable to legalize artifacts. However, it’s possible to combine them after processing the rest of the instruction because the legalization is likely to generate more artifacts that allow ArtifactCombiner to combine away them. Instead, move illegal artifacts to another list called RetryList and wait until all of the instruction in InstList are legalized. After that, check if there is any new artifacts and try to combine them again if that’s the case. If not, abort. The idea is similar to D59339, but the approach is a bit different. This patch fixes the issue described above, but the legalizer still may be unable to handle some cases depending on when to legalize artifacts. So, in the long run, we probably need a different legalization strategy that handles this dependency in a better way. Reviewers: dsanders, aditya_nandakumar, qcolombet, arsenm, aemerson, paquette Reviewed By: dsanders Subscribers: jvesely, wdng, nhaehnle, rovka, javed.absar, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65894 llvm-svn: 369805
2019-08-24 04:30:35 +08:00
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
AMDGPU/GlobalISel: Legalize select for v4s16 Also add some more select tests to help show future legalization changes. llvm-svn: 353045
2019-02-04 22:04:52 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 0
%2:_(<2 x s32>) = COPY $vgpr1_vgpr2
%3:_(<2 x s32>) = COPY $vgpr3_vgpr4
%4:_(<2 x s8>) = G_TRUNC %2
%5:_(<2 x s8>) = G_TRUNC %3
%6:_(s1) = G_ICMP intpred(ne), %0, %1
%7:_(<2 x s8>) = G_SELECT %6, %4, %5
%8:_(<2 x s32>) = G_ANYEXT %7
$vgpr0_vgpr1 = COPY %8
...
---
name: test_select_v3s8
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6
; CHECK-LABEL: name: test_select_v3s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr1_vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr4_vgpr5_vgpr6
; CHECK: [[TRUNC:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[COPY1]](<3 x s32>)
; CHECK: [[TRUNC1:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[COPY2]](<3 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
GlobalISel: Implement moreElementsVector for select llvm-svn: 354354
2019-02-20 01:03:09 +08:00
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s8>) = G_IMPLICIT_DEF
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s8>) = G_INSERT [[DEF]], [[TRUNC]](<3 x s8>), 0
GlobalISel: Don't handle widenScalar for vector G_INSERT This handling didn't make any sense for vectors.
2020-07-19 00:27:16 +08:00
; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s8>) = G_INSERT [[DEF]], [[TRUNC1]](<3 x s8>), 0
GlobalISel: Implement moreElementsVector for select llvm-svn: 354354
2019-02-20 01:03:09 +08:00
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[INSERT]](<4 x s8>)
GlobalISel: Don't handle widenScalar for vector G_INSERT This handling didn't make any sense for vectors.
2020-07-19 00:27:16 +08:00
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[INSERT1]](<4 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT]], [[ANYEXT1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT2]], [[ANYEXT3]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT1]](s16)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)
; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT4]], [[ANYEXT5]]
; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT2]](s16)
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)
; CHECK: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT6]], [[ANYEXT7]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT3]](s16)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s8>) = G_BUILD_VECTOR [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8)
GlobalISel: Reimplement moreElementsVectorDst Use pad with undef and unmerge with unused results. This is annoyingly similar to several other places in LegalizerHelper, but they're all slightly different.
2020-02-03 06:42:02 +08:00
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s8>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<4 x s8>), [[DEF]](<4 x s8>), [[DEF]](<4 x s8>)
; CHECK: [[UV8:%[0-9]+]]:_(<3 x s8>), [[UV9:%[0-9]+]]:_(<3 x s8>), [[UV10:%[0-9]+]]:_(<3 x s8>), [[UV11:%[0-9]+]]:_(<3 x s8>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<12 x s8>)
; CHECK: [[ANYEXT8:%[0-9]+]]:_(<3 x s32>) = G_ANYEXT [[UV8]](<3 x s8>)
GlobalISel: Don't handle widenScalar for vector G_INSERT This handling didn't make any sense for vectors.
2020-07-19 00:27:16 +08:00
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[ANYEXT8]](<3 x s32>)
AMDGPU/GlobalISel: Legalize select for v4s16 Also add some more select tests to help show future legalization changes. llvm-svn: 353045
2019-02-04 22:04:52 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 0
%2:_(<3 x s32>) = COPY $vgpr1_vgpr2_vgpr3
%3:_(<3 x s32>) = COPY $vgpr4_vgpr5_vgpr6
%4:_(<3 x s8>) = G_TRUNC %2
%5:_(<3 x s8>) = G_TRUNC %3
%6:_(s1) = G_ICMP intpred(ne), %0, %1
%7:_(<3 x s8>) = G_SELECT %6, %4, %5
%8:_(<3 x s32>) = G_ANYEXT %7
$vgpr0_vgpr1_vgpr2 = COPY %8
...
---
name: test_select_v4s8
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: test_select_v4s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC G_BITCAST can be lowered with a pair of G_UNMERGE_VALUES and G_MERGE_VALUES with different types, but G_UNMERGE_VALUES of a vector can also be implemented with a bitcast to a scalar, which introduces the possibility for infinite loops. Try to eliminate an illegal source register type in the artifact combiner to avoid this from happening. Avoids infinite looping in the legalizer in a future patch which allows lowering G_UNMERGE_VALUES of a vector source with a G_BITCAST.
2020-04-05 03:07:28 +08:00
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV4]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC2]], [[TRUNC3]]
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC4]], [[TRUNC5]]
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC6]], [[TRUNC7]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT2]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT3]](s16)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
[GlobalISel] Legalizer: Retry combining illegal artifacts as long as there new artifacts Summary: Currently, Legalizer aborts if it’s unable to legalize artifacts. However, it’s possible to combine them after processing the rest of the instruction because the legalization is likely to generate more artifacts that allow ArtifactCombiner to combine away them. Instead, move illegal artifacts to another list called RetryList and wait until all of the instruction in InstList are legalized. After that, check if there is any new artifacts and try to combine them again if that’s the case. If not, abort. The idea is similar to D59339, but the approach is a bit different. This patch fixes the issue described above, but the legalizer still may be unable to handle some cases depending on when to legalize artifacts. So, in the long run, we probably need a different legalization strategy that handles this dependency in a better way. Reviewers: dsanders, aditya_nandakumar, qcolombet, arsenm, aemerson, paquette Reviewed By: dsanders Subscribers: jvesely, wdng, nhaehnle, rovka, javed.absar, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65894 llvm-svn: 369805
2019-08-24 04:30:35 +08:00
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
AMDGPU/GlobalISel: Legalize select for v4s16 Also add some more select tests to help show future legalization changes. llvm-svn: 353045
2019-02-04 22:04:52 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 0
%2:_(<4 x s32>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%3:_(<4 x s32>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%4:_(<4 x s8>) = G_TRUNC %2
%5:_(<4 x s8>) = G_TRUNC %3
%6:_(s1) = G_ICMP intpred(ne), %0, %1
%7:_(<4 x s8>) = G_SELECT %6, %4, %5
%8:_(<4 x s32>) = G_ANYEXT %7
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %8
...
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
---
name: test_select_v2s16
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: test_select_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[C]]
; CHECK: [[SELECT:%[0-9]+]]:_(<2 x s16>) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
; CHECK: $vgpr0 = COPY [[SELECT]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
%3:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(ne), %2, %3
%5:_(<2 x s16>) = G_SELECT %4, %0, %1
$vgpr0 = COPY %5
...
AMDGPU/GlobalISel: Legalize select for v4s16 Also add some more select tests to help show future legalization changes. llvm-svn: 353045
2019-02-04 22:04:52 +08:00
---
name: test_select_v3s16
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
; CHECK-LABEL: name: test_select_v3s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr3_vgpr4
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY1]](<4 x s16>), 0
; CHECK: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY2]](<4 x s16>), 0
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
GlobalISel: Implement moreElementsVector for select llvm-svn: 354354
2019-02-20 01:03:09 +08:00
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
GlobalISel: Allow CSE of G_IMPLICIT_DEF The legalizer produces a lot of these, and they make reading legalized MIR annoying. For some reason, this does seem to sometimes introduce copies of implicit def, which is dumb.
2020-02-04 11:49:00 +08:00
; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT1]](<3 x s16>), 0
GlobalISel: Implement moreElementsVector for select llvm-svn: 354354
2019-02-20 01:03:09 +08:00
; CHECK: [[SELECT:%[0-9]+]]:_(<4 x s16>) = G_SELECT [[ICMP]](s1), [[INSERT]], [[INSERT1]]
GlobalISel: Reimplement moreElementsVectorDst Use pad with undef and unmerge with unused results. This is annoyingly similar to several other places in LegalizerHelper, but they're all slightly different.
2020-02-03 06:42:02 +08:00
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[SELECT]](<4 x s16>), [[DEF]](<4 x s16>), [[DEF]](<4 x s16>)
; CHECK: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>), [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<12 x s16>)
; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV]](<3 x s16>), 0
GlobalISel: Implement moreElementsVector for select llvm-svn: 354354
2019-02-20 01:03:09 +08:00
; CHECK: $vgpr0_vgpr1 = COPY [[INSERT2]](<4 x s16>)
AMDGPU/GlobalISel: Legalize select for v4s16 Also add some more select tests to help show future legalization changes. llvm-svn: 353045
2019-02-04 22:04:52 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s16>) = COPY $vgpr1_vgpr2
%2:_(<4 x s16>) = COPY $vgpr3_vgpr4
%4:_(s32) = G_CONSTANT i32 0
%5:_(s1) = G_ICMP intpred(ne), %0, %4
%6:_(<3 x s16>) = G_EXTRACT %1, 0
%7:_(<3 x s16>) = G_EXTRACT %2, 0
%8:_(<3 x s16>) = G_SELECT %5, %6, %7
%9:_(<4 x s16>) = G_IMPLICIT_DEF
%10:_(<4 x s16>) = G_INSERT %9, %8, 0
$vgpr0_vgpr1 = COPY %10
...
---
name: test_select_v4s16
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
; CHECK-LABEL: name: test_select_v4s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr3_vgpr4
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[SELECT:%[0-9]+]]:_(<4 x s16>) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](<4 x s16>)
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s16>) = COPY $vgpr1_vgpr2
%2:_(<4 x s16>) = COPY $vgpr3_vgpr4
%4:_(s32) = G_CONSTANT i32 0
%5:_(s1) = G_ICMP intpred(ne), %0, %4
%6:_(<4 x s16>) = G_SELECT %5, %1, %2
$vgpr0_vgpr1 = COPY %6
...
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
---
name: test_select_v2s32
body: |
bb.0:
GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANT llvm-svn: 351853
2019-01-23 02:53:41 +08:00
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK-LABEL: name: test_select_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANT llvm-svn: 351853
2019-01-23 02:53:41 +08:00
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr3_vgpr4
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[SELECT:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](<2 x s32>)
GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANT llvm-svn: 351853
2019-01-23 02:53:41 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(<2 x s32>) = COPY $vgpr1_vgpr2
%2:_(<2 x s32>) = COPY $vgpr3_vgpr4
%4:_(s32) = G_CONSTANT i32 0
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANT llvm-svn: 351853
2019-01-23 02:53:41 +08:00
%5:_(s1) = G_ICMP intpred(ne), %0, %4
%6:_(<2 x s32>) = G_SELECT %5, %1, %2
$vgpr0_vgpr1 = COPY %6
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
...
GlobalISel: Implement fewerElementsVector for select llvm-svn: 352601
2019-01-30 12:19:31 +08:00
---
name: test_select_v3s32
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6
; CHECK-LABEL: name: test_select_v3s32
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr1_vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr4_vgpr5_vgpr6
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV3]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV4]]
; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV2]], [[UV5]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32), [[SELECT2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(<3 x s32>) = COPY $vgpr1_vgpr2_vgpr3
%3:_(<3 x s32>) = COPY $vgpr4_vgpr5_vgpr6
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<3 x s32>) = G_SELECT %4, %2, %3
$vgpr0_vgpr1_vgpr2 = COPY %5
...
---
name: test_select_v4s32
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: test_select_v4s32
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(<2 x s32>), [[UV3:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[SELECT]](<2 x s32>), [[SELECT1]](<2 x s32>)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(<4 x s32>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%3:_(<4 x s32>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<4 x s32>) = G_SELECT %4, %2, %3
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5
...
---
name: test_select_v2s64
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: test_select_v2s64
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY2]](<2 x s64>)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(<2 x s64>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%3:_(<2 x s64>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<2 x s64>) = G_SELECT %4, %2, %3
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5
...
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
---
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
name: test_select_p0
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
body: |
bb.0:
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
; CHECK-LABEL: name: test_select_p0
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY $vgpr3_vgpr4
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](p0)
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%2:_(p0) = COPY $vgpr1_vgpr2
%3:_(p0) = COPY $vgpr3_vgpr4
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p0) = G_SELECT %4, %2, %3
$vgpr0_vgpr1 = COPY %5
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
...
---
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
name: test_select_p1
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
body: |
bb.0:
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
; CHECK-LABEL: name: test_select_p1
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(p1) = COPY $vgpr3_vgpr4
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK: [[SELECT:%[0-9]+]]:_(p1) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](p1)
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%2:_(p1) = COPY $vgpr1_vgpr2
%3:_(p1) = COPY $vgpr3_vgpr4
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p1) = G_SELECT %4, %2, %3
$vgpr0_vgpr1 = COPY %5
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
...
---
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
name: test_select_p2
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
body: |
bb.0:
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: test_select_p2
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK: [[COPY1:%[0-9]+]]:_(p2) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(p2) = COPY $vgpr2
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK: [[SELECT:%[0-9]+]]:_(p2) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0 = COPY [[SELECT]](p2)
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%2:_(p2) = COPY $vgpr1
%3:_(p2) = COPY $vgpr2
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p2) = G_SELECT %4, %2, %3
$vgpr0 = COPY %5
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
...
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
---
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
name: test_select_p3
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
body: |
bb.0:
GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANT llvm-svn: 351853
2019-01-23 02:53:41 +08:00
liveins: $vgpr0, $vgpr1, $vgpr2
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK-LABEL: name: test_select_p3
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0 = COPY [[SELECT]](p3)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(p3) = COPY $vgpr1
%3:_(p3) = COPY $vgpr2
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p3) = G_SELECT %4, %2, %3
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
$vgpr0 = COPY %5
...
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
---
name: test_select_p4
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
; CHECK-LABEL: name: test_select_p4
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(p4) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(p4) = COPY $vgpr3_vgpr4
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[SELECT:%[0-9]+]]:_(p4) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](p4)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(p4) = COPY $vgpr1_vgpr2
%3:_(p4) = COPY $vgpr3_vgpr4
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p4) = G_SELECT %4, %2, %3
$vgpr0_vgpr1 = COPY %5
...
---
name: test_select_p5
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
GlobalISel: Implement narrowScalar for select Don't handle vector conditions. I think this can be merged in the future with fewerElementsVectorSelect, although this becomes slightly tricky with a vector condition. llvm-svn: 353122
2019-02-05 08:13:44 +08:00
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK-LABEL: name: test_select_p5
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(p5) = COPY $vgpr2
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[SELECT:%[0-9]+]]:_(p5) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0 = COPY [[SELECT]](p5)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(p5) = COPY $vgpr1
%3:_(p5) = COPY $vgpr2
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p5) = G_SELECT %4, %2, %3
$vgpr0 = COPY %5
...
---
name: test_select_p999
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
GlobalISel: Implement narrowScalar for select Don't handle vector conditions. I think this can be merged in the future with fewerElementsVectorSelect, although this becomes slightly tricky with a vector condition. llvm-svn: 353122
2019-02-05 08:13:44 +08:00
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK-LABEL: name: test_select_p999
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(p999) = COPY $vgpr3_vgpr4
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[SELECT:%[0-9]+]]:_(p999) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](p999)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(p999) = COPY $vgpr1_vgpr2
%3:_(p999) = COPY $vgpr3_vgpr4
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p999) = G_SELECT %4, %2, %3
$vgpr0_vgpr1 = COPY %5
...
---
GlobalISel: Implement narrowScalar for select Don't handle vector conditions. I think this can be merged in the future with fewerElementsVectorSelect, although this becomes slightly tricky with a vector condition. llvm-svn: 353122
2019-02-05 08:13:44 +08:00
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
name: test_select_v2p3
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
; CHECK-LABEL: name: test_select_v2p3
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr3_vgpr4
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[SELECT:%[0-9]+]]:_(<2 x p3>) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](<2 x p3>)
%0:_(s32) = COPY $vgpr0
%1:_(<2 x p3>) = COPY $vgpr1_vgpr2
%2:_(<2 x p3>) = COPY $vgpr3_vgpr4
%4:_(s32) = G_CONSTANT i32 0
%5:_(s1) = G_ICMP intpred(ne), %0, %4
%6:_(<2 x p3>) = G_SELECT %5, %1, %2
$vgpr0_vgpr1 = COPY %6
...
---
name: test_select_v3p3
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6
; CHECK-LABEL: name: test_select_v3p3
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x p3>) = COPY $vgpr1_vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x p3>) = COPY $vgpr4_vgpr5_vgpr6
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3), [[UV2:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<3 x p3>)
; CHECK: [[UV3:%[0-9]+]]:_(p3), [[UV4:%[0-9]+]]:_(p3), [[UV5:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY2]](<3 x p3>)
; CHECK: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[UV]], [[UV3]]
; CHECK: [[SELECT1:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV4]]
; CHECK: [[SELECT2:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[UV2]], [[UV5]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x p3>) = G_BUILD_VECTOR [[SELECT]](p3), [[SELECT1]](p3), [[SELECT2]](p3)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x p3>)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(<3 x p3>) = COPY $vgpr1_vgpr2_vgpr3
%3:_(<3 x p3>) = COPY $vgpr4_vgpr5_vgpr6
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<3 x p3>) = G_SELECT %4, %2, %3
$vgpr0_vgpr1_vgpr2 = COPY %5
...
---
name: test_select_v4p3
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: test_select_v4p3
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x p3>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x p3>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[UV:%[0-9]+]]:_(<2 x p3>), [[UV1:%[0-9]+]]:_(<2 x p3>) = G_UNMERGE_VALUES [[COPY1]](<4 x p3>)
; CHECK: [[UV2:%[0-9]+]]:_(<2 x p3>), [[UV3:%[0-9]+]]:_(<2 x p3>) = G_UNMERGE_VALUES [[COPY2]](<4 x p3>)
; CHECK: [[SELECT:%[0-9]+]]:_(<2 x p3>) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:_(<2 x p3>) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x p3>) = G_CONCAT_VECTORS [[SELECT]](<2 x p3>), [[SELECT1]](<2 x p3>)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x p3>)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(<4 x p3>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%3:_(<4 x p3>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<4 x p3>) = G_SELECT %4, %2, %3
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5
...
---
name: test_select_v4p5
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: test_select_v4p5
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x p5>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x p5>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[UV:%[0-9]+]]:_(<2 x p5>), [[UV1:%[0-9]+]]:_(<2 x p5>) = G_UNMERGE_VALUES [[COPY1]](<4 x p5>)
; CHECK: [[UV2:%[0-9]+]]:_(<2 x p5>), [[UV3:%[0-9]+]]:_(<2 x p5>) = G_UNMERGE_VALUES [[COPY2]](<4 x p5>)
; CHECK: [[SELECT:%[0-9]+]]:_(<2 x p5>) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:_(<2 x p5>) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x p5>) = G_CONCAT_VECTORS [[SELECT]](<2 x p5>), [[SELECT1]](<2 x p5>)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x p5>)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(<4 x p5>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%3:_(<4 x p5>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<4 x p5>) = G_SELECT %4, %2, %3
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5
...
---
name: test_select_v2p0
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: test_select_v2p0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY1]](<2 x p0>)
; CHECK: [[UV2:%[0-9]+]]:_(p0), [[UV3:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY2]](<2 x p0>)
; CHECK: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[SELECT]](p0), [[SELECT1]](p0)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p0>)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(<2 x p0>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%3:_(<2 x p0>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<2 x p0>) = G_SELECT %4, %2, %3
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5
...
---
name: test_select_v4p0
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8, $vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16
; CHECK-LABEL: name: test_select_v4p0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x p0>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x p0>) = COPY $vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0), [[UV2:%[0-9]+]]:_(p0), [[UV3:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY1]](<4 x p0>)
; CHECK: [[UV4:%[0-9]+]]:_(p0), [[UV5:%[0-9]+]]:_(p0), [[UV6:%[0-9]+]]:_(p0), [[UV7:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY2]](<4 x p0>)
; CHECK: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV]], [[UV4]]
; CHECK: [[SELECT1:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV5]]
; CHECK: [[SELECT2:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV2]], [[UV6]]
; CHECK: [[SELECT3:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV3]], [[UV7]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x p0>) = G_BUILD_VECTOR [[SELECT]](p0), [[SELECT1]](p0), [[SELECT2]](p0), [[SELECT3]](p0)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x p0>)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(<4 x p0>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
%3:_(<4 x p0>) = COPY $vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<4 x p0>) = G_SELECT %4, %2, %3
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %5
...
---
GlobalISel: Implement narrowScalar for select Don't handle vector conditions. I think this can be merged in the future with fewerElementsVectorSelect, although this becomes slightly tricky with a vector condition. llvm-svn: 353122
2019-02-05 08:13:44 +08:00
name: test_select_v2s96
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_select_v2s96
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s96>) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(<2 x s96>) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[UV:%[0-9]+]]:_(s96), [[UV1:%[0-9]+]]:_(s96) = G_UNMERGE_VALUES [[DEF]](<2 x s96>)
; CHECK: [[UV2:%[0-9]+]]:_(s96), [[UV3:%[0-9]+]]:_(s96) = G_UNMERGE_VALUES [[DEF1]](<2 x s96>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[UV]](s96), 0
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[UV]](s96), 64
; CHECK: [[EXTRACT2:%[0-9]+]]:_(s64) = G_EXTRACT [[UV2]](s96), 0
; CHECK: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[UV2]](s96), 64
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[EXTRACT]], [[EXTRACT2]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[EXTRACT1]], [[EXTRACT3]]
; CHECK: [[DEF2:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF
GlobalISel: Allow CSE of G_IMPLICIT_DEF The legalizer produces a lot of these, and they make reading legalized MIR annoying. For some reason, this does seem to sometimes introduce copies of implicit def, which is dumb.
2020-02-04 11:49:00 +08:00
; CHECK: [[COPY1:%[0-9]+]]:_(s96) = COPY [[DEF2]](s96)
; CHECK: [[INSERT:%[0-9]+]]:_(s96) = G_INSERT [[COPY1]], [[SELECT]](s64), 0
GlobalISel: Implement narrowScalar for select Don't handle vector conditions. I think this can be merged in the future with fewerElementsVectorSelect, although this becomes slightly tricky with a vector condition. llvm-svn: 353122
2019-02-05 08:13:44 +08:00
; CHECK: [[INSERT1:%[0-9]+]]:_(s96) = G_INSERT [[INSERT]], [[SELECT1]](s32), 64
; CHECK: [[EXTRACT4:%[0-9]+]]:_(s64) = G_EXTRACT [[UV1]](s96), 0
; CHECK: [[EXTRACT5:%[0-9]+]]:_(s32) = G_EXTRACT [[UV1]](s96), 64
; CHECK: [[EXTRACT6:%[0-9]+]]:_(s64) = G_EXTRACT [[UV3]](s96), 0
; CHECK: [[EXTRACT7:%[0-9]+]]:_(s32) = G_EXTRACT [[UV3]](s96), 64
; CHECK: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[EXTRACT4]], [[EXTRACT6]]
; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[EXTRACT5]], [[EXTRACT7]]
GlobalISel: Allow CSE of G_IMPLICIT_DEF The legalizer produces a lot of these, and they make reading legalized MIR annoying. For some reason, this does seem to sometimes introduce copies of implicit def, which is dumb.
2020-02-04 11:49:00 +08:00
; CHECK: [[INSERT2:%[0-9]+]]:_(s96) = G_INSERT [[DEF2]], [[SELECT2]](s64), 0
GlobalISel: Implement narrowScalar for select Don't handle vector conditions. I think this can be merged in the future with fewerElementsVectorSelect, although this becomes slightly tricky with a vector condition. llvm-svn: 353122
2019-02-05 08:13:44 +08:00
; CHECK: [[INSERT3:%[0-9]+]]:_(s96) = G_INSERT [[INSERT2]], [[SELECT3]](s32), 64
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s96>) = G_BUILD_VECTOR [[INSERT1]](s96), [[INSERT3]](s96)
; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s96>)
%0:_(<2 x s96>) = G_IMPLICIT_DEF
%1:_(<2 x s96>) = G_IMPLICIT_DEF
%2:_(s32) = COPY $vgpr0
%3:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(ne), %2, %3
%5:_(<2 x s96>) = G_SELECT %4, %0, %1
S_NOP 0, implicit %5
...
---
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
name: test_select_v8p0
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_select_v8p0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[DEF:%[0-9]+]]:_(<8 x p0>) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(<8 x p0>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0), [[UV2:%[0-9]+]]:_(p0), [[UV3:%[0-9]+]]:_(p0), [[UV4:%[0-9]+]]:_(p0), [[UV5:%[0-9]+]]:_(p0), [[UV6:%[0-9]+]]:_(p0), [[UV7:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[DEF]](<8 x p0>)
; CHECK: [[UV8:%[0-9]+]]:_(p0), [[UV9:%[0-9]+]]:_(p0), [[UV10:%[0-9]+]]:_(p0), [[UV11:%[0-9]+]]:_(p0), [[UV12:%[0-9]+]]:_(p0), [[UV13:%[0-9]+]]:_(p0), [[UV14:%[0-9]+]]:_(p0), [[UV15:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[DEF1]](<8 x p0>)
; CHECK: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV]], [[UV8]]
; CHECK: [[SELECT1:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV9]]
; CHECK: [[SELECT2:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV2]], [[UV10]]
; CHECK: [[SELECT3:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV3]], [[UV11]]
; CHECK: [[SELECT4:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV4]], [[UV12]]
; CHECK: [[SELECT5:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV5]], [[UV13]]
; CHECK: [[SELECT6:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV6]], [[UV14]]
; CHECK: [[SELECT7:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV7]], [[UV15]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x p0>) = G_BUILD_VECTOR [[SELECT]](p0), [[SELECT1]](p0), [[SELECT2]](p0), [[SELECT3]](p0), [[SELECT4]](p0), [[SELECT5]](p0), [[SELECT6]](p0), [[SELECT7]](p0)
; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<8 x p0>)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(<8 x p0>) = G_IMPLICIT_DEF
%3:_(<8 x p0>) = G_IMPLICIT_DEF
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<8 x p0>) = G_SELECT %4, %2, %3
S_NOP 0, implicit %5
GlobalISel: Implement narrowScalar for select Don't handle vector conditions. I think this can be merged in the future with fewerElementsVectorSelect, although this becomes slightly tricky with a vector condition. llvm-svn: 353122
2019-02-05 08:13:44 +08:00
...
---
name: test_select_v2s128
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16
; CHECK-LABEL: name: test_select_v2s128
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[C]]
; CHECK: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>)
; CHECK: [[UV2:%[0-9]+]]:_(s128), [[UV3:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY1]](<2 x s128>)
; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; CHECK: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV2]](s128)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[UV4]], [[UV6]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[UV5]], [[UV7]]
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT1]](s64)
; CHECK: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; CHECK: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV3]](s128)
; CHECK: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[UV8]], [[UV10]]
; CHECK: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[UV9]], [[UV11]]
; CHECK: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT2]](s64), [[SELECT3]](s64)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
%0:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ,
%1:_(<2 x s128>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
%2:_(s32) = COPY $vgpr16
%3:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(ne), %2, %3
%5:_(<2 x s128>) = G_SELECT %4, %0, %1
[AMDGPU] Fix formatting in MIR tests
2020-07-02 17:17:03 +08:00
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %5
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
...
---
name: test_vselect_v2s32
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
; CHECK-LABEL: name: test_vselect_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr6_vgpr7
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV4]], [[UV6]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[UV5]], [[UV7]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s32>) = COPY $vgpr4_vgpr5
%3:_(<2 x s32>) = COPY $vgpr6_vgpr7
%4:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
%5:_(<2 x s32>) = G_SELECT %4, %2, %3
$vgpr0_vgpr1 = COPY %5
...
GlobalISel: Implement fewerElementsVector for select llvm-svn: 352601
2019-01-30 12:19:31 +08:00
---
name: test_vselect_v3s32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: test_vselect_v3s32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV6]], [[UV9]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[UV7]], [[UV10]]
; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[UV8]], [[UV11]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32), [[SELECT2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
%2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
%3:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
%4:_(<3 x s32>) = G_SELECT %3, %1, %2
$vgpr0_vgpr1_vgpr2 = COPY %4
...
---
name: test_vselect_v4s32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; CHECK-LABEL: name: test_vselect_v4s32
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV4]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV5]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV6]]
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV3]](s32), [[UV7]]
; CHECK: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
; CHECK: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV8]], [[UV12]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[UV9]], [[UV13]]
; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[UV10]], [[UV14]]
; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[UV11]], [[UV15]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32), [[SELECT2]](s32), [[SELECT3]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
%2:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
%3:_(<4 x s1>) = G_ICMP intpred(ne), %0, %1
%4:_(<4 x s32>) = G_SELECT %3, %1, %2
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4
...
---
name: test_vselect_v2s64
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; CHECK-LABEL: name: test_vselect_v2s64
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s64), [[UV2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s64), [[UV3]]
; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; CHECK: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY2]](<2 x s64>)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[UV4]], [[UV6]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV5]], [[UV7]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
%2:_(<2 x s64>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
%3:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
%4:_(<2 x s64>) = G_SELECT %3, %1, %2
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4
...
---
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
name: test_vselect_v2p3
GlobalISel: Implement fewerElementsVector for select llvm-svn: 352601
2019-01-30 12:19:31 +08:00
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK-LABEL: name: test_vselect_v2p3
GlobalISel: Implement fewerElementsVector for select llvm-svn: 352601
2019-01-30 12:19:31 +08:00
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr4_vgpr5
; CHECK: [[COPY3:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr6_vgpr7
GlobalISel: Implement fewerElementsVector for select llvm-svn: 352601
2019-01-30 12:19:31 +08:00
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
; CHECK: [[UV4:%[0-9]+]]:_(p3), [[UV5:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY2]](<2 x p3>)
; CHECK: [[UV6:%[0-9]+]]:_(p3), [[UV7:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY3]](<2 x p3>)
; CHECK: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[UV4]], [[UV6]]
; CHECK: [[SELECT1:%[0-9]+]]:_(p3) = G_SELECT [[ICMP1]](s1), [[UV5]], [[UV7]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[SELECT]](p3), [[SELECT1]](p3)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
GlobalISel: Implement fewerElementsVector for select llvm-svn: 352601
2019-01-30 12:19:31 +08:00
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%2:_(<2 x p3>) = COPY $vgpr4_vgpr5
%3:_(<2 x p3>) = COPY $vgpr6_vgpr7
GlobalISel: Implement fewerElementsVector for select llvm-svn: 352601
2019-01-30 12:19:31 +08:00
%4:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
%5:_(<2 x p3>) = G_SELECT %4, %2, %3
GlobalISel: Implement fewerElementsVector for select llvm-svn: 352601
2019-01-30 12:19:31 +08:00
$vgpr0_vgpr1 = COPY %5
...
AMDGPU/GlobalISel: Legalize select for pointer types llvm-svn: 352974
2019-02-03 07:31:50 +08:00
---
name: test_vselect_v2p0
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11, $vgpr12_vgpr13_vgpr14_vgpr15
; CHECK-LABEL: name: test_vselect_v2p0
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
; CHECK: [[COPY3:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr12_vgpr13_vgpr14_vgpr15
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s64), [[UV2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s64), [[UV3]]
; CHECK: [[UV4:%[0-9]+]]:_(p0), [[UV5:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY2]](<2 x p0>)
; CHECK: [[UV6:%[0-9]+]]:_(p0), [[UV7:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY3]](<2 x p0>)
; CHECK: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[UV4]], [[UV6]]
; CHECK: [[SELECT1:%[0-9]+]]:_(p0) = G_SELECT [[ICMP1]](s1), [[UV5]], [[UV7]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[SELECT]](p0), [[SELECT1]](p0)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p0>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
%2:_(<2 x p0>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
%3:_(<2 x p0>) = COPY $vgpr12_vgpr13_vgpr14_vgpr15
%4:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
%5:_(<2 x p0>) = G_SELECT %4, %2, %3
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5
...
AMDGPU/GlobalISel: Fix legalizing <3 x s16> vselects
2020-04-12 03:59:51 +08:00
---
name: test_vselect_v3s8
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8, $vgpr9_vgpr10_vgpr11
; CHECK-LABEL: name: test_vselect_v3s8
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
; CHECK: [[COPY3:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC G_BITCAST can be lowered with a pair of G_UNMERGE_VALUES and G_MERGE_VALUES with different types, but G_UNMERGE_VALUES of a vector can also be implemented with a bitcast to a scalar, which introduces the possibility for infinite loops. Try to eliminate an illegal source register type in the artifact combiner to avoid this from happening. Avoids infinite looping in the legalizer in a future patch which allows lowering G_UNMERGE_VALUES of a vector source with a G_BITCAST.
2020-04-05 03:07:28 +08:00
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<3 x s32>)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV9]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV10]](s32)
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[TRUNC2]], [[TRUNC3]]
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV8]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV11]](s32)
; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP2]](s1), [[TRUNC4]], [[TRUNC5]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT2]](s16)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
AMDGPU/GlobalISel: Fix legalizing <3 x s16> vselects
2020-04-12 03:59:51 +08:00
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
%2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
%3:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11
%4:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
%5:_(<3 x s8>) = G_TRUNC %2
%6:_(<3 x s8>) = G_TRUNC %3
%7:_(<3 x s8>) = G_SELECT %4, %5, %6
%8:_(<3 x s32>) = G_ANYEXT %7
$vgpr0_vgpr1_vgpr2 = COPY %8
...
---
name: test_vselect_v3s16
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8, $vgpr9_vgpr10_vgpr11
; CHECK-LABEL: name: test_vselect_v3s16
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
; CHECK: [[COPY3:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC G_BITCAST can be lowered with a pair of G_UNMERGE_VALUES and G_MERGE_VALUES with different types, but G_UNMERGE_VALUES of a vector can also be implemented with a bitcast to a scalar, which introduces the possibility for infinite loops. Try to eliminate an illegal source register type in the artifact combiner to avoid this from happening. Avoids infinite looping in the legalizer in a future patch which allows lowering G_UNMERGE_VALUES of a vector source with a G_BITCAST.
2020-04-05 03:07:28 +08:00
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV8]](s32)
AMDGPU/GlobalISel: Fix legalizing <3 x s16> vselects
2020-04-12 03:59:51 +08:00
; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<3 x s32>)
GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC G_BITCAST can be lowered with a pair of G_UNMERGE_VALUES and G_MERGE_VALUES with different types, but G_UNMERGE_VALUES of a vector can also be implemented with a bitcast to a scalar, which introduces the possibility for infinite loops. Try to eliminate an illegal source register type in the artifact combiner to avoid this from happening. Avoids infinite looping in the legalizer in a future patch which allows lowering G_UNMERGE_VALUES of a vector source with a G_BITCAST.
2020-04-05 03:07:28 +08:00
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV9]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV10]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV11]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC3]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[TRUNC1]], [[TRUNC4]]
; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP2]](s1), [[TRUNC2]], [[TRUNC5]]
AMDGPU/GlobalISel: Fix legalizing <3 x s16> vselects
2020-04-12 03:59:51 +08:00
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT1]](s16)
GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC G_BITCAST can be lowered with a pair of G_UNMERGE_VALUES and G_MERGE_VALUES with different types, but G_UNMERGE_VALUES of a vector can also be implemented with a bitcast to a scalar, which introduces the possibility for infinite loops. Try to eliminate an illegal source register type in the artifact combiner to avoid this from happening. Avoids infinite looping in the legalizer in a future patch which allows lowering G_UNMERGE_VALUES of a vector source with a G_BITCAST.
2020-04-05 03:07:28 +08:00
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
AMDGPU/GlobalISel: Fix legalizing <3 x s16> vselects
2020-04-12 03:59:51 +08:00
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC G_BITCAST can be lowered with a pair of G_UNMERGE_VALUES and G_MERGE_VALUES with different types, but G_UNMERGE_VALUES of a vector can also be implemented with a bitcast to a scalar, which introduces the possibility for infinite loops. Try to eliminate an illegal source register type in the artifact combiner to avoid this from happening. Avoids infinite looping in the legalizer in a future patch which allows lowering G_UNMERGE_VALUES of a vector source with a G_BITCAST.
2020-04-05 03:07:28 +08:00
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
AMDGPU/GlobalISel: Fix legalizing <3 x s16> vselects
2020-04-12 03:59:51 +08:00
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT2]](s16)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC G_BITCAST can be lowered with a pair of G_UNMERGE_VALUES and G_MERGE_VALUES with different types, but G_UNMERGE_VALUES of a vector can also be implemented with a bitcast to a scalar, which introduces the possibility for infinite loops. Try to eliminate an illegal source register type in the artifact combiner to avoid this from happening. Avoids infinite looping in the legalizer in a future patch which allows lowering G_UNMERGE_VALUES of a vector source with a G_BITCAST.
2020-04-05 03:07:28 +08:00
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
; CHECK: [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV12]](<2 x s16>)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
AMDGPU/GlobalISel: Fix legalizing <3 x s16> vselects
2020-04-12 03:59:51 +08:00
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
%2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
%3:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11
%4:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
%5:_(<3 x s16>) = G_TRUNC %2
%6:_(<3 x s16>) = G_TRUNC %3
%7:_(<3 x s16>) = G_SELECT %4, %5, %6
%8:_(<3 x s32>) = G_ANYEXT %7
$vgpr0_vgpr1_vgpr2 = COPY %8
...