2018-10-23 06:52:23 +08:00
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# RUN: llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass branch-folder | FileCheck %s
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# Check that we do not generate invalid MIR when optimizing condjumps with undef
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# flags on the eflags input (currently we should just bail out).
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---
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# CHECK-LABEL: name: fallundef
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name: fallundef
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tracksRegLiveness: true
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body: |
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bb.0:
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
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JCC_1 %bb.1, 4, implicit undef $eflags
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; CHECK: JCC_1 %bb.1, 4, implicit undef $eflags
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2018-10-23 06:52:23 +08:00
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JMP_1 %bb.2
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bb.1:
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RET 2, undef $eax
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bb.2:
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RET 0, undef $eax
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...
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