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llvm-project/llvm/test/CodeGen/PowerPC/mulld.ll

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Remove trailing whitespace introduced in r342440. llvm-svn: 342463
2018-09-18 18:53:13 +08:00
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
[PowerPC][NFC] Add a mulld testcase for scheduling check. This patch add a mulld testcase for scheduling check. Patch By: jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D52039 llvm-svn: 342440
2018-09-18 09:59:22 +08:00
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-ITIN
Remove trailing whitespace introduced in r342440. llvm-svn: 342463
2018-09-18 18:53:13 +08:00
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
[PowerPC][NFC] Add a mulld testcase for scheduling check. This patch add a mulld testcase for scheduling check. Patch By: jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D52039 llvm-svn: 342440
2018-09-18 09:59:22 +08:00
; RUN: --check-prefix=CHECK-ITIN
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-ITIN
define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* nocapture readonly %b) {
; CHECK-LABEL: bn_mul_comba8:
; CHECK: mulhdu
; CHECK-NEXT: mulld
[Power9] Enable the Out-of-Order scheduling model for P9 hw When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
2019-01-03 13:04:18 +08:00
; CHECK: mulhdu
; CHECK: mulld
[PowerPC][NFC] Add a mulld testcase for scheduling check. This patch add a mulld testcase for scheduling check. Patch By: jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D52039 llvm-svn: 342440
2018-09-18 09:59:22 +08:00
; CHECK-NEXT: mulhdu
; CHECK-ITIN-LABEL: bn_mul_comba8:
; CHECK-ITIN: mulhdu
; CHECK-ITIN-NEXT: mulld
; CHECK-ITIN-NEXT: mulhdu
; CHECK-ITIN-NEXT: mulld
[PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch By: jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D52040 llvm-svn: 342441
2018-09-18 10:05:18 +08:00
; CHECK-ITIN-NEXT: mulhdu
[PowerPC][NFC] Add a mulld testcase for scheduling check. This patch add a mulld testcase for scheduling check. Patch By: jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D52039 llvm-svn: 342440
2018-09-18 09:59:22 +08:00
%1 = load i64, i64* %a, align 8
%conv = zext i64 %1 to i128
%2 = load i64, i64* %b, align 8
%conv2 = zext i64 %2 to i128
%mul = mul nuw i128 %conv2, %conv
%shr = lshr i128 %mul, 64
%agep = getelementptr inbounds i64, i64* %a, i64 1
%3 = load i64, i64* %agep, align 8
%conv14 = zext i64 %3 to i128
%mul15 = mul nuw i128 %conv14, %conv
%add17 = add i128 %mul15, %shr
%shr19 = lshr i128 %add17, 64
%conv20 = trunc i128 %shr19 to i64
%bgep = getelementptr inbounds i64, i64* %b, i64 1
%4 = load i64, i64* %bgep, align 8
%conv28 = zext i64 %4 to i128
%mul31 = mul nuw i128 %conv28, %conv2
%conv32 = and i128 %add17, 18446744073709551615
%add33 = add i128 %conv32, %mul31
%shr35 = lshr i128 %add33, 64
%conv36 = trunc i128 %shr35 to i64
%add37 = add i64 %conv36, %conv20
%cmp38 = icmp ult i64 %add37, %conv36
%conv148 = zext i1 %cmp38 to i64
store i64 %conv148, i64* %r, align 8
ret void
}