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llvm-project/llvm/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll

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[PowerPC] Support operand modifier 'x' in inline asm gcc uses operand modifier 'x' in inline asm for VSX registers. Without this modifier, instructions which use VSX numbering for their operands are printed as VMX registers. This patch adds support for the operand modifier 'x'. Differential Revision: https://reviews.llvm.org/D52244 llvm-svn: 342882
2018-09-24 22:01:16 +08:00
; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
define signext i32 @foo(<4 x float> %__A) {
entry:
%0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3;\0Axscvspdp ${1:x},${1:x};\0Afctiw $1,$1;\0Amfvsrd $0,${1:x};\0A", "=r,=&^wa,^wa"(<4 x float> %__A)
%asmresult = extractvalue { i32, <4 x float> } %0, 0
ret i32 %asmresult
Fixed a typo in the test s/CEHCK/CHECK/ Summary: Turns out the test was not correct, I had to adjust the test to work. I also added CHECK-LABELs for better error messages from FileCheck while I'm here. Reviewers: jsji Subscribers: nemanjai, eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58614 llvm-svn: 355079
2019-02-28 18:56:39 +08:00
; CHECK-LABEL: foo:
[PowerPC] Support operand modifier 'x' in inline asm gcc uses operand modifier 'x' in inline asm for VSX registers. Without this modifier, instructions which use VSX numbering for their operands are printed as VMX registers. This patch adds support for the operand modifier 'x'. Differential Revision: https://reviews.llvm.org/D52244 llvm-svn: 342882
2018-09-24 22:01:16 +08:00
; CHECK: #APP
; CHECK: xxsldwi vs0, v2, v2, 3
; CHECK: xscvspdp f0, f0
; CHECK: fctiw f0, f0
; CHECK: mffprd r3, f0
; CHECK: #NO_APP
}
[PowerPC] Support constraint 'wi' in asm From the gcc manual, we can see that the specific limit of wi inline asm is “FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS”. The link is https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Machine-Constraints.html#Machine-Constraints. We should accept this constraint. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D53265 llvm-svn: 345810
2018-11-01 10:35:17 +08:00
define signext i32 @foo1(<4 x float> %__A) {
entry:
%0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3;\0Axscvspdp ${1:x},${1:x};\0Afctiw $1,$1;\0Amfvsrd $0,${1:x};\0A", "=r,=&^wi,^wa"(<4 x float> %__A)
%asmresult = extractvalue { i32, <4 x float> } %0, 0
ret i32 %asmresult
Fixed a typo in the test s/CEHCK/CHECK/ Summary: Turns out the test was not correct, I had to adjust the test to work. I also added CHECK-LABELs for better error messages from FileCheck while I'm here. Reviewers: jsji Subscribers: nemanjai, eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58614 llvm-svn: 355079
2019-02-28 18:56:39 +08:00
; CHECK-LABEL: foo1:
[PowerPC] Support constraint 'wi' in asm From the gcc manual, we can see that the specific limit of wi inline asm is “FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS”. The link is https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Machine-Constraints.html#Machine-Constraints. We should accept this constraint. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D53265 llvm-svn: 345810
2018-11-01 10:35:17 +08:00
; CHECK: #APP
; CHECK: xxsldwi vs0, v2, v2, 3
; CHECK: xscvspdp f0, f0
Fixed a typo in the test s/CEHCK/CHECK/ Summary: Turns out the test was not correct, I had to adjust the test to work. I also added CHECK-LABELs for better error messages from FileCheck while I'm here. Reviewers: jsji Subscribers: nemanjai, eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58614 llvm-svn: 355079
2019-02-28 18:56:39 +08:00
; CHECK: fctiw f0, f0
[PowerPC] Support constraint 'wi' in asm From the gcc manual, we can see that the specific limit of wi inline asm is “FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS”. The link is https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Machine-Constraints.html#Machine-Constraints. We should accept this constraint. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D53265 llvm-svn: 345810
2018-11-01 10:35:17 +08:00
; CHECK: mffprd r3, f0
; CHECK: #NO_APP
Fixed a typo in the test s/CEHCK/CHECK/ Summary: Turns out the test was not correct, I had to adjust the test to work. I also added CHECK-LABELs for better error messages from FileCheck while I'm here. Reviewers: jsji Subscribers: nemanjai, eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58614 llvm-svn: 355079
2019-02-28 18:56:39 +08:00
; CHECK: extsw r3, r3
[PowerPC] Support constraint 'wi' in asm From the gcc manual, we can see that the specific limit of wi inline asm is “FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS”. The link is https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Machine-Constraints.html#Machine-Constraints. We should accept this constraint. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D53265 llvm-svn: 345810
2018-11-01 10:35:17 +08:00
}
[PowerPC] Support operand modifier 'x' in inline asm gcc uses operand modifier 'x' in inline asm for VSX registers. Without this modifier, instructions which use VSX numbering for their operands are printed as VMX registers. This patch adds support for the operand modifier 'x'. Differential Revision: https://reviews.llvm.org/D52244 llvm-svn: 342882
2018-09-24 22:01:16 +08:00
define double @test() {
entry:
%0 = tail call double asm "mtvsrd ${0:x}, 1", "=^ws,~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14}"()
ret double %0
Fixed a typo in the test s/CEHCK/CHECK/ Summary: Turns out the test was not correct, I had to adjust the test to work. I also added CHECK-LABELs for better error messages from FileCheck while I'm here. Reviewers: jsji Subscribers: nemanjai, eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58614 llvm-svn: 355079
2019-02-28 18:56:39 +08:00
; CHECK-LABEL: test:
[PowerPC] Support operand modifier 'x' in inline asm gcc uses operand modifier 'x' in inline asm for VSX registers. Without this modifier, instructions which use VSX numbering for their operands are printed as VMX registers. This patch adds support for the operand modifier 'x'. Differential Revision: https://reviews.llvm.org/D52244 llvm-svn: 342882
2018-09-24 22:01:16 +08:00
; CHECK: #APP
; CHECK: mtvsrd v2, r1
; CHECK: #NO_APP
}