2019-03-18 04:36:12 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
|
|
|
; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,SI
|
|
|
|
|
; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,VI
|
2016-11-16 11:16:26 +08:00
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @select_f16(
|
2019-03-18 04:36:12 +08:00
|
|
|
; SI-LABEL: select_f16:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s15, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s14, -1
|
|
|
|
|
; SI-NEXT: s_mov_b32 s22, s14
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s16, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s17, s11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s10, s14
|
|
|
|
|
; SI-NEXT: s_mov_b32 s11, s15
|
|
|
|
|
; SI-NEXT: s_mov_b32 s20, s6
|
|
|
|
|
; SI-NEXT: s_mov_b32 s21, s7
|
|
|
|
|
; SI-NEXT: s_mov_b32 s23, s15
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, s14
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, s15
|
|
|
|
|
; SI-NEXT: s_mov_b32 s18, s14
|
|
|
|
|
; SI-NEXT: s_mov_b32 s19, s15
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v0, off, s[20:23], 0
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v2, off, s[16:19], 0
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v3, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s12, s4
|
|
|
|
|
; SI-NEXT: s_mov_b32 s13, s5
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
|
|
|
|
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[12:15], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: select_f16:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s14, s2
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; VI-NEXT: s_mov_b32 s16, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s17, s11
|
|
|
|
|
; VI-NEXT: s_mov_b32 s4, s6
|
|
|
|
|
; VI-NEXT: s_mov_b32 s5, s7
|
|
|
|
|
; VI-NEXT: s_mov_b32 s10, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s11, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s15, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s18, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s19, s3
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v2, off, s[16:19], 0
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
|
|
|
|
|
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-11-16 11:16:26 +08:00
|
|
|
half addrspace(1)* %r,
|
|
|
|
|
half addrspace(1)* %a,
|
|
|
|
|
half addrspace(1)* %b,
|
|
|
|
|
half addrspace(1)* %c,
|
|
|
|
|
half addrspace(1)* %d) {
|
|
|
|
|
entry:
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
%a.val = load volatile half, half addrspace(1)* %a
|
|
|
|
|
%b.val = load volatile half, half addrspace(1)* %b
|
|
|
|
|
%c.val = load volatile half, half addrspace(1)* %c
|
|
|
|
|
%d.val = load volatile half, half addrspace(1)* %d
|
2016-11-16 11:16:26 +08:00
|
|
|
%fcmp = fcmp olt half %a.val, %b.val
|
|
|
|
|
%r.val = select i1 %fcmp, half %c.val, half %d.val
|
|
|
|
|
store half %r.val, half addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @select_f16_imm_a(
|
2019-03-18 04:36:12 +08:00
|
|
|
; SI-LABEL: select_f16_imm_a:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; SI-NEXT: s_mov_b32 s18, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s19, s11
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s16, s2
|
|
|
|
|
; SI-NEXT: s_mov_b32 s17, s3
|
|
|
|
|
; SI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; SI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; SI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_cmp_lt_f32_e32 vcc, 0.5, v0
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: select_f16_imm_a:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, s11
|
|
|
|
|
; VI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; VI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; VI-NEXT: v_cmp_lt_f16_e32 vcc, 0.5, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
|
|
|
|
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-11-16 11:16:26 +08:00
|
|
|
half addrspace(1)* %r,
|
|
|
|
|
half addrspace(1)* %b,
|
|
|
|
|
half addrspace(1)* %c,
|
|
|
|
|
half addrspace(1)* %d) {
|
|
|
|
|
entry:
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
%b.val = load volatile half, half addrspace(1)* %b
|
|
|
|
|
%c.val = load volatile half, half addrspace(1)* %c
|
|
|
|
|
%d.val = load volatile half, half addrspace(1)* %d
|
2016-11-16 11:16:26 +08:00
|
|
|
%fcmp = fcmp olt half 0xH3800, %b.val
|
|
|
|
|
%r.val = select i1 %fcmp, half %c.val, half %d.val
|
|
|
|
|
store half %r.val, half addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @select_f16_imm_b(
|
2019-03-18 04:36:12 +08:00
|
|
|
; SI-LABEL: select_f16_imm_b:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; SI-NEXT: s_mov_b32 s18, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s19, s11
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s16, s2
|
|
|
|
|
; SI-NEXT: s_mov_b32 s17, s3
|
|
|
|
|
; SI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; SI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; SI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0.5, v0
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: select_f16_imm_b:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, s11
|
|
|
|
|
; VI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; VI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; VI-NEXT: v_cmp_gt_f16_e32 vcc, 0.5, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
|
|
|
|
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-11-16 11:16:26 +08:00
|
|
|
half addrspace(1)* %r,
|
|
|
|
|
half addrspace(1)* %a,
|
|
|
|
|
half addrspace(1)* %c,
|
|
|
|
|
half addrspace(1)* %d) {
|
|
|
|
|
entry:
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
%a.val = load volatile half, half addrspace(1)* %a
|
|
|
|
|
%c.val = load volatile half, half addrspace(1)* %c
|
|
|
|
|
%d.val = load volatile half, half addrspace(1)* %d
|
2016-11-16 11:16:26 +08:00
|
|
|
%fcmp = fcmp olt half %a.val, 0xH3800
|
|
|
|
|
%r.val = select i1 %fcmp, half %c.val, half %d.val
|
|
|
|
|
store half %r.val, half addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @select_f16_imm_c(
|
2019-03-18 04:36:12 +08:00
|
|
|
; SI-LABEL: select_f16_imm_c:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; SI-NEXT: s_mov_b32 s18, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s19, s11
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; SI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s16, s2
|
|
|
|
|
; SI-NEXT: s_mov_b32 s17, s3
|
|
|
|
|
; SI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v0, v1
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, 0.5, v2, vcc
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: select_f16_imm_c:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; VI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, s11
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, 0x3800
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v1
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
|
|
|
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-11-16 11:16:26 +08:00
|
|
|
half addrspace(1)* %r,
|
|
|
|
|
half addrspace(1)* %a,
|
|
|
|
|
half addrspace(1)* %b,
|
|
|
|
|
half addrspace(1)* %d) {
|
|
|
|
|
entry:
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
%a.val = load volatile half, half addrspace(1)* %a
|
|
|
|
|
%b.val = load volatile half, half addrspace(1)* %b
|
|
|
|
|
%d.val = load volatile half, half addrspace(1)* %d
|
2016-11-16 11:16:26 +08:00
|
|
|
%fcmp = fcmp olt half %a.val, %b.val
|
|
|
|
|
%r.val = select i1 %fcmp, half 0xH3800, half %d.val
|
|
|
|
|
store half %r.val, half addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @select_f16_imm_d(
|
2019-03-18 04:36:12 +08:00
|
|
|
; SI-LABEL: select_f16_imm_d:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; SI-NEXT: s_mov_b32 s18, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s19, s11
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; SI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s16, s2
|
|
|
|
|
; SI-NEXT: s_mov_b32 s17, s3
|
|
|
|
|
; SI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, 0.5, v2, vcc
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: select_f16_imm_d:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; VI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, s11
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[4:7], 0
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, 0x3800
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
|
|
|
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-11-16 11:16:26 +08:00
|
|
|
half addrspace(1)* %r,
|
|
|
|
|
half addrspace(1)* %a,
|
|
|
|
|
half addrspace(1)* %b,
|
|
|
|
|
half addrspace(1)* %c) {
|
|
|
|
|
entry:
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
%a.val = load volatile half, half addrspace(1)* %a
|
|
|
|
|
%b.val = load volatile half, half addrspace(1)* %b
|
|
|
|
|
%c.val = load volatile half, half addrspace(1)* %c
|
2016-11-16 11:16:26 +08:00
|
|
|
%fcmp = fcmp olt half %a.val, %b.val
|
|
|
|
|
%r.val = select i1 %fcmp, half %c.val, half 0xH3800
|
|
|
|
|
store half %r.val, half addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @select_v2f16(
|
2019-03-18 04:36:12 +08:00
|
|
|
; SI-LABEL: select_v2f16:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s15, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s14, -1
|
|
|
|
|
; SI-NEXT: s_mov_b32 s22, s14
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s16, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s17, s11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s10, s14
|
|
|
|
|
; SI-NEXT: s_mov_b32 s11, s15
|
|
|
|
|
; SI-NEXT: s_mov_b32 s20, s6
|
|
|
|
|
; SI-NEXT: s_mov_b32 s21, s7
|
|
|
|
|
; SI-NEXT: s_mov_b32 s23, s15
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, s14
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, s15
|
|
|
|
|
; SI-NEXT: buffer_load_dword v0, off, s[20:23], 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s18, s14
|
|
|
|
|
; SI-NEXT: s_mov_b32 s19, s15
|
|
|
|
|
; SI-NEXT: buffer_load_dword v1, off, s[8:11], 0
|
|
|
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: buffer_load_dword v3, off, s[16:19], 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s12, s4
|
|
|
|
|
; SI-NEXT: s_mov_b32 s13, s5
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v2
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
|
|
|
|
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v5, v6
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
|
|
|
|
|
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[12:15], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: select_v2f16:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s14, s2
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; VI-NEXT: s_mov_b32 s16, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s17, s11
|
|
|
|
|
; VI-NEXT: s_mov_b32 s4, s6
|
|
|
|
|
; VI-NEXT: s_mov_b32 s5, s7
|
|
|
|
|
; VI-NEXT: s_mov_b32 s10, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s11, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s15, s3
|
|
|
|
|
; VI-NEXT: buffer_load_dword v0, off, s[4:7], 0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s18, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s19, s3
|
|
|
|
|
; VI-NEXT: buffer_load_dword v1, off, s[8:11], 0
|
|
|
|
|
; VI-NEXT: buffer_load_dword v2, off, s[12:15], 0
|
|
|
|
|
; VI-NEXT: buffer_load_dword v3, off, s[16:19], 0
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(3)
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
|
|
|
|
|
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v6, v5
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
|
|
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-11-16 11:16:26 +08:00
|
|
|
<2 x half> addrspace(1)* %r,
|
|
|
|
|
<2 x half> addrspace(1)* %a,
|
|
|
|
|
<2 x half> addrspace(1)* %b,
|
|
|
|
|
<2 x half> addrspace(1)* %c,
|
|
|
|
|
<2 x half> addrspace(1)* %d) {
|
|
|
|
|
entry:
|
|
|
|
|
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
|
|
|
|
|
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
|
|
|
|
|
%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
|
|
|
|
|
%d.val = load <2 x half>, <2 x half> addrspace(1)* %d
|
|
|
|
|
%fcmp = fcmp olt <2 x half> %a.val, %b.val
|
|
|
|
|
%r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> %d.val
|
|
|
|
|
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @select_v2f16_imm_a(
|
2019-03-18 04:36:12 +08:00
|
|
|
; SI-LABEL: select_v2f16_imm_a:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; SI-NEXT: s_mov_b32 s18, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s19, s11
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s16, s2
|
|
|
|
|
; SI-NEXT: s_mov_b32 s17, s3
|
|
|
|
|
; SI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; SI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; SI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; SI-NEXT: buffer_load_dword v0, off, s[16:19], 0
|
|
|
|
|
; SI-NEXT: buffer_load_dword v1, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: buffer_load_dword v2, off, s[12:15], 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, 0x3f200000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc
|
|
|
|
|
; SI-NEXT: v_cmp_lt_f32_e32 vcc, 0.5, v0
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: select_v2f16_imm_a:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, s11
|
|
|
|
|
; VI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; VI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: buffer_load_dword v1, off, s[4:7], 0
|
|
|
|
|
; VI-NEXT: buffer_load_dword v2, off, s[12:15], 0
|
|
|
|
|
; VI-NEXT: s_movk_i32 s0, 0x3900
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
|
|
|
|
; VI-NEXT: v_cmp_lt_f16_e32 vcc, 0.5, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
|
|
|
; VI-NEXT: v_cmp_lt_f16_e32 vcc, s0, v3
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
|
|
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-11-16 11:16:26 +08:00
|
|
|
<2 x half> addrspace(1)* %r,
|
|
|
|
|
<2 x half> addrspace(1)* %b,
|
|
|
|
|
<2 x half> addrspace(1)* %c,
|
|
|
|
|
<2 x half> addrspace(1)* %d) {
|
|
|
|
|
entry:
|
|
|
|
|
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
|
|
|
|
|
%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
|
|
|
|
|
%d.val = load <2 x half>, <2 x half> addrspace(1)* %d
|
|
|
|
|
%fcmp = fcmp olt <2 x half> <half 0xH3800, half 0xH3900>, %b.val
|
|
|
|
|
%r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> %d.val
|
|
|
|
|
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @select_v2f16_imm_b(
|
2019-03-18 04:36:12 +08:00
|
|
|
; SI-LABEL: select_v2f16_imm_b:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; SI-NEXT: s_mov_b32 s18, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s19, s11
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s16, s2
|
|
|
|
|
; SI-NEXT: s_mov_b32 s17, s3
|
|
|
|
|
; SI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; SI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; SI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; SI-NEXT: buffer_load_dword v0, off, s[16:19], 0
|
|
|
|
|
; SI-NEXT: buffer_load_dword v1, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: buffer_load_dword v2, off, s[12:15], 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, 0x3f200000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc
|
|
|
|
|
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0.5, v0
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: select_v2f16_imm_b:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, s11
|
|
|
|
|
; VI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; VI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: buffer_load_dword v1, off, s[4:7], 0
|
|
|
|
|
; VI-NEXT: buffer_load_dword v2, off, s[12:15], 0
|
|
|
|
|
; VI-NEXT: s_movk_i32 s0, 0x3900
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
|
|
|
|
; VI-NEXT: v_cmp_gt_f16_e32 vcc, 0.5, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
|
|
|
; VI-NEXT: v_cmp_gt_f16_e32 vcc, s0, v3
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
|
|
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-11-16 11:16:26 +08:00
|
|
|
<2 x half> addrspace(1)* %r,
|
|
|
|
|
<2 x half> addrspace(1)* %a,
|
|
|
|
|
<2 x half> addrspace(1)* %c,
|
|
|
|
|
<2 x half> addrspace(1)* %d) {
|
|
|
|
|
entry:
|
|
|
|
|
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
|
|
|
|
|
%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
|
|
|
|
|
%d.val = load <2 x half>, <2 x half> addrspace(1)* %d
|
|
|
|
|
%fcmp = fcmp olt <2 x half> %a.val, <half 0xH3800, half 0xH3900>
|
|
|
|
|
%r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> %d.val
|
|
|
|
|
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @select_v2f16_imm_c(
|
2019-03-18 04:36:12 +08:00
|
|
|
; SI-LABEL: select_v2f16_imm_c:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; SI-NEXT: s_mov_b32 s18, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s19, s11
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; SI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s16, s2
|
|
|
|
|
; SI-NEXT: s_mov_b32 s17, s3
|
|
|
|
|
; SI-NEXT: buffer_load_dword v3, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; SI-NEXT: buffer_load_dword v0, off, s[16:19], 0
|
|
|
|
|
; SI-NEXT: buffer_load_dword v1, off, s[12:15], 0
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, 0x3f200000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v0
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
|
|
|
; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v0, v5
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc
|
|
|
|
|
; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v4, v3
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, 0.5, v1, vcc
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: select_v2f16_imm_c:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; VI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, s11
|
|
|
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: buffer_load_dword v4, off, s[4:7], 0
|
|
|
|
|
; VI-NEXT: buffer_load_dword v1, off, s[12:15], 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, 0x3800
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, 0x3900
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v4
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
|
|
|
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v6, v5
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
|
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-11-16 11:16:26 +08:00
|
|
|
<2 x half> addrspace(1)* %r,
|
|
|
|
|
<2 x half> addrspace(1)* %a,
|
|
|
|
|
<2 x half> addrspace(1)* %b,
|
|
|
|
|
<2 x half> addrspace(1)* %d) {
|
|
|
|
|
entry:
|
|
|
|
|
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
|
|
|
|
|
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
|
|
|
|
|
%d.val = load <2 x half>, <2 x half> addrspace(1)* %d
|
|
|
|
|
%fcmp = fcmp olt <2 x half> %a.val, %b.val
|
|
|
|
|
%r.val = select <2 x i1> %fcmp, <2 x half> <half 0xH3800, half 0xH3900>, <2 x half> %d.val
|
|
|
|
|
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @select_v2f16_imm_d(
|
2019-03-18 04:36:12 +08:00
|
|
|
; SI-LABEL: select_v2f16_imm_d:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; SI-NEXT: s_mov_b32 s18, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s19, s11
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; SI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s16, s2
|
|
|
|
|
; SI-NEXT: s_mov_b32 s17, s3
|
|
|
|
|
; SI-NEXT: buffer_load_dword v3, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; SI-NEXT: buffer_load_dword v0, off, s[16:19], 0
|
|
|
|
|
; SI-NEXT: buffer_load_dword v1, off, s[12:15], 0
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, 0x3f200000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
|
|
|
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v4, v5
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
|
|
|
|
|
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v3
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, 0.5, v1, vcc
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: select_v2f16_imm_d:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_mov_b32 s11, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s10, -1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s14, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s15, s11
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s8, s0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s9, s1
|
|
|
|
|
; VI-NEXT: s_mov_b32 s12, s6
|
|
|
|
|
; VI-NEXT: s_mov_b32 s13, s7
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, s11
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, s10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, s11
|
|
|
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: buffer_load_dword v4, off, s[4:7], 0
|
|
|
|
|
; VI-NEXT: buffer_load_dword v1, off, s[12:15], 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, 0x3800
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, 0x3900
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
|
|
|
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v4
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
|
|
|
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v6, v5
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
|
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-11-16 11:16:26 +08:00
|
|
|
<2 x half> addrspace(1)* %r,
|
|
|
|
|
<2 x half> addrspace(1)* %a,
|
|
|
|
|
<2 x half> addrspace(1)* %b,
|
|
|
|
|
<2 x half> addrspace(1)* %c) {
|
|
|
|
|
entry:
|
|
|
|
|
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
|
|
|
|
|
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
|
|
|
|
|
%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
|
|
|
|
|
%fcmp = fcmp olt <2 x half> %a.val, %b.val
|
|
|
|
|
%r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> <half 0xH3800, half 0xH3900>
|
|
|
|
|
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|