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llvm-project/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll

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[mips][msa] Summarize tests Adds a comment to the start of each test summarizing the area the test covers. llvm-svn: 189465
2013-08-28 18:02:29 +08:00
; Test the MSA intrinsics that are encoded with the 2R instruction format and
; convert scalars to vectors.
[mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200399
2014-01-29 22:32:03 +08:00
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
[mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
2014-01-29 23:12:02 +08:00
; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64
; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
@llvm_mips_fill_b_ARG1 = global i32 23, align 16
@llvm_mips_fill_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_fill_b_test() nounwind {
entry:
%0 = load i32* @llvm_mips_fill_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.fill.b(i32 %0)
store <16 x i8> %1, <16 x i8>* @llvm_mips_fill_b_RES
ret void
}
declare <16 x i8> @llvm.mips.fill.b(i32) nounwind
[mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200399
2014-01-29 22:32:03 +08:00
; MIPS-ANY: llvm_mips_fill_b_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]],
[mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
2014-01-29 23:12:02 +08:00
; MIPS64-DAG: ld [[R1:\$[0-9]+]],
[mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200399
2014-01-29 22:32:03 +08:00
; MIPS-ANY-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]]
; MIPS-ANY-DAG: st.b [[R2]],
; MIPS-ANY: .size llvm_mips_fill_b_test
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
;
@llvm_mips_fill_h_ARG1 = global i32 23, align 16
@llvm_mips_fill_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
define void @llvm_mips_fill_h_test() nounwind {
entry:
%0 = load i32* @llvm_mips_fill_h_ARG1
%1 = tail call <8 x i16> @llvm.mips.fill.h(i32 %0)
store <8 x i16> %1, <8 x i16>* @llvm_mips_fill_h_RES
ret void
}
declare <8 x i16> @llvm.mips.fill.h(i32) nounwind
[mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200399
2014-01-29 22:32:03 +08:00
; MIPS-ANY: llvm_mips_fill_h_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]],
[mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
2014-01-29 23:12:02 +08:00
; MIPS64-DAG: ld [[R1:\$[0-9]+]],
[mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200399
2014-01-29 22:32:03 +08:00
; MIPS-ANY-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]]
; MIPS-ANY-DAG: st.h [[R2]],
; MIPS-ANY: .size llvm_mips_fill_h_test
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
;
@llvm_mips_fill_w_ARG1 = global i32 23, align 16
@llvm_mips_fill_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
define void @llvm_mips_fill_w_test() nounwind {
entry:
%0 = load i32* @llvm_mips_fill_w_ARG1
%1 = tail call <4 x i32> @llvm.mips.fill.w(i32 %0)
store <4 x i32> %1, <4 x i32>* @llvm_mips_fill_w_RES
ret void
}
declare <4 x i32> @llvm.mips.fill.w(i32) nounwind
[mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200399
2014-01-29 22:32:03 +08:00
; MIPS-ANY: llvm_mips_fill_w_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]],
[mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
2014-01-29 23:12:02 +08:00
; MIPS64-DAG: ld [[R1:\$[0-9]+]],
[mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200399
2014-01-29 22:32:03 +08:00
; MIPS-ANY-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]]
; MIPS-ANY-DAG: st.w [[R2]],
; MIPS-ANY: .size llvm_mips_fill_w_test
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
;
[mips][msa] Implemented fill.d intrinsic. This intrinsic is lowered into an equivalent BUILD_VECTOR which is further lowered into a sequence of insert.w's on MIPS32. llvm-svn: 191519
2013-09-27 21:20:41 +08:00
@llvm_mips_fill_d_ARG1 = global i64 23, align 16
@llvm_mips_fill_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
define void @llvm_mips_fill_d_test() nounwind {
entry:
%0 = load i64* @llvm_mips_fill_d_ARG1
%1 = tail call <2 x i64> @llvm.mips.fill.d(i64 %0)
store <2 x i64> %1, <2 x i64>* @llvm_mips_fill_d_RES
ret void
}
declare <2 x i64> @llvm.mips.fill.d(i64) nounwind
[mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200399
2014-01-29 22:32:03 +08:00
; MIPS-ANY: llvm_mips_fill_d_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]], 0(
; MIPS32-DAG: lw [[R2:\$[0-9]+]], 4(
[mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
2014-01-29 23:12:02 +08:00
; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_fill_d_ARG1)
[mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200399
2014-01-29 22:32:03 +08:00
; MIPS32-DAG: ldi.b [[R3:\$w[0-9]+]], 0
; MIPS32-DAG: insert.w [[R3]][0], [[R1]]
; MIPS32-DAG: insert.w [[R3]][1], [[R2]]
; MIPS32-DAG: insert.w [[R3]][2], [[R1]]
; MIPS32-DAG: insert.w [[R3]][3], [[R2]]
[mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
2014-01-29 23:12:02 +08:00
; MIPS64-DAG: fill.d [[WD:\$w[0-9]+]], [[R1]]
[mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200399
2014-01-29 22:32:03 +08:00
; MIPS32-DAG: st.w [[R3]],
[mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
2014-01-29 23:12:02 +08:00
; MIPS64-DAG: ld [[RD:\$[0-9]+]], %got_disp(llvm_mips_fill_d_RES)
; MIPS64-DAG: st.d [[WD]], 0([[RD]])
[mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200399
2014-01-29 22:32:03 +08:00
; MIPS-ANY: .size llvm_mips_fill_d_test
[mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
2014-01-29 23:12:02 +08:00
;