2017-02-17 02:15:16 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
2016-10-24 23:43:40 +08:00
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
|
Reapply r165661, Patch by Shuxin Yang <shuxin.llvm@gmail.com>.
Original message:
The attached is the fix to radar://11663049. The optimization can be outlined by following rules:
(select (x != c), e, c) -> select (x != c), e, x),
(select (x == c), c, e) -> select (x == c), x, e)
where the <c> is an integer constant.
The reason for this change is that : on x86, conditional-move-from-constant needs two instructions;
however, conditional-move-from-register need only one instruction.
While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase.
The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource".
Original message since r165661:
My previous change has a bug: I negated the condition code of a CMOV, and go ahead creating a new CMOV using the *ORIGINAL* condition code.
llvm-svn: 166017
2012-10-16 14:28:34 +08:00
|
|
|
|
2017-02-17 02:15:16 +08:00
|
|
|
; Select of constants: control flow / conditional moves can always be replaced by logic+math (but may not be worth it?).
|
|
|
|
; Test the zeroext/signext variants of each pattern to see if that makes a difference.
|
|
|
|
|
|
|
|
; select Cond, 0, 1 --> zext (!Cond)
|
|
|
|
|
2016-10-25 03:13:29 +08:00
|
|
|
define i32 @select_0_or_1(i1 %cond) {
|
|
|
|
; CHECK-LABEL: select_0_or_1:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2016-10-25 03:13:29 +08:00
|
|
|
; CHECK-NEXT: notb %dil
|
|
|
|
; CHECK-NEXT: movzbl %dil, %eax
|
|
|
|
; CHECK-NEXT: andl $1, %eax
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 0, i32 1
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @select_0_or_1_zeroext(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_0_or_1_zeroext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2016-10-25 03:13:29 +08:00
|
|
|
; CHECK-NEXT: xorb $1, %dil
|
|
|
|
; CHECK-NEXT: movzbl %dil, %eax
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 0, i32 1
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
2017-02-17 02:15:16 +08:00
|
|
|
define i32 @select_0_or_1_signext(i1 signext %cond) {
|
|
|
|
; CHECK-LABEL: select_0_or_1_signext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: notb %dil
|
|
|
|
; CHECK-NEXT: movzbl %dil, %eax
|
|
|
|
; CHECK-NEXT: andl $1, %eax
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 0, i32 1
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
; select Cond, 1, 0 --> zext (Cond)
|
|
|
|
|
2016-10-25 03:13:29 +08:00
|
|
|
define i32 @select_1_or_0(i1 %cond) {
|
|
|
|
; CHECK-LABEL: select_1_or_0:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2016-10-25 03:13:29 +08:00
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-NEXT: andl $1, %eax
|
2016-10-25 03:13:29 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 1, i32 0
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_1_or_0_zeroext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-09-19 06:05:35 +08:00
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
2016-10-25 03:13:29 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 1, i32 0
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
2017-02-17 02:15:16 +08:00
|
|
|
define i32 @select_1_or_0_signext(i1 signext %cond) {
|
|
|
|
; CHECK-LABEL: select_1_or_0_signext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-10-09 23:22:20 +08:00
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-NEXT: andl $1, %eax
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 1, i32 0
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
; select Cond, 0, -1 --> sext (!Cond)
|
|
|
|
|
2016-10-25 03:13:29 +08:00
|
|
|
define i32 @select_0_or_neg1(i1 %cond) {
|
|
|
|
; CHECK-LABEL: select_0_or_neg1:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
|
2016-10-25 03:13:29 +08:00
|
|
|
; CHECK-NEXT: andl $1, %edi
|
|
|
|
; CHECK-NEXT: leal -1(%rdi), %eax
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 0, i32 -1
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_0_or_neg1_zeroext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
|
2017-09-19 06:05:35 +08:00
|
|
|
; CHECK-NEXT: leal -1(%rdi), %eax
|
2016-10-25 03:13:29 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 0, i32 -1
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
2017-02-17 02:15:16 +08:00
|
|
|
define i32 @select_0_or_neg1_signext(i1 signext %cond) {
|
|
|
|
; CHECK-LABEL: select_0_or_neg1_signext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-10-09 23:22:20 +08:00
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-NEXT: notl %eax
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 0, i32 -1
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
; select Cond, -1, 0 --> sext (Cond)
|
|
|
|
|
2016-10-25 03:13:29 +08:00
|
|
|
define i32 @select_neg1_or_0(i1 %cond) {
|
|
|
|
; CHECK-LABEL: select_neg1_or_0:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-02-25 01:17:33 +08:00
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-NEXT: andl $1, %eax
|
|
|
|
; CHECK-NEXT: negl %eax
|
2016-10-25 03:13:29 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 -1, i32 0
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_neg1_or_0_zeroext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-09-19 06:05:35 +08:00
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-NEXT: negl %eax
|
2016-10-25 03:13:29 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 -1, i32 0
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
2017-02-17 02:15:16 +08:00
|
|
|
define i32 @select_neg1_or_0_signext(i1 signext %cond) {
|
|
|
|
; CHECK-LABEL: select_neg1_or_0_signext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-10-09 23:22:20 +08:00
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 -1, i32 0
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
; select Cond, C+1, C --> add (zext Cond), C
|
|
|
|
|
|
|
|
define i32 @select_Cplus1_C(i1 %cond) {
|
|
|
|
; CHECK-LABEL: select_Cplus1_C:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: andl $1, %edi
|
|
|
|
; CHECK-NEXT: leal 41(%rdi), %eax
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 42, i32 41
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_Cplus1_C_zeroext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
|
2017-09-19 06:05:35 +08:00
|
|
|
; CHECK-NEXT: leal 41(%rdi), %eax
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 42, i32 41
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @select_Cplus1_C_signext(i1 signext %cond) {
|
|
|
|
; CHECK-LABEL: select_Cplus1_C_signext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-10-09 23:22:20 +08:00
|
|
|
; CHECK-NEXT: movl $41, %eax
|
|
|
|
; CHECK-NEXT: subl %edi, %eax
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 42, i32 41
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
; select Cond, C, C+1 --> add (sext Cond), C
|
|
|
|
|
|
|
|
define i32 @select_C_Cplus1(i1 %cond) {
|
|
|
|
; CHECK-LABEL: select_C_Cplus1:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
[DAGCombiner] allow transforming (select Cond, C +/- 1, C) to (add(ext Cond), C)
select Cond, C +/- 1, C --> add(ext Cond), C -- with a target hook.
This is part of the ongoing process to obsolete D24480. The motivation is to
canonicalize to select IR in InstCombine whenever possible, so we need to have a way to
undo that easily in codegen.
PowerPC is an obvious winner for this kind of transform because it has fast and complete
bit-twiddling abilities but generally lousy conditional execution perf (although this might
have changed in recent implementations).
x86 also sees some wins, but the effect is limited because these transforms already mostly
exist in its target-specific combineSelectOfTwoConstants(). The fact that we see any x86
changes just shows that that code is a mess of special-case holes. We may be able to remove
some of that logic now.
My guess is that other targets will want to enable this hook for most cases. The likely
follow-ups would be to add value type and/or the constants themselves as parameters for the
hook. As the tests in select_const.ll show, we can transform any select-of-constants to
math/logic, but the general transform for any 2 constants needs one more instruction
(multiply or 'and').
ARM is one target that I think may not want this for most cases. I see infinite loops there
because it wants to use selects to enable conditionally executed instructions.
Differential Revision: https://reviews.llvm.org/D30537
llvm-svn: 296977
2017-03-05 03:18:09 +08:00
|
|
|
; CHECK-NEXT: andl $1, %edi
|
|
|
|
; CHECK-NEXT: movl $42, %eax
|
|
|
|
; CHECK-NEXT: subl %edi, %eax
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 41, i32 42
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_C_Cplus1_zeroext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
[DAGCombiner] allow transforming (select Cond, C +/- 1, C) to (add(ext Cond), C)
select Cond, C +/- 1, C --> add(ext Cond), C -- with a target hook.
This is part of the ongoing process to obsolete D24480. The motivation is to
canonicalize to select IR in InstCombine whenever possible, so we need to have a way to
undo that easily in codegen.
PowerPC is an obvious winner for this kind of transform because it has fast and complete
bit-twiddling abilities but generally lousy conditional execution perf (although this might
have changed in recent implementations).
x86 also sees some wins, but the effect is limited because these transforms already mostly
exist in its target-specific combineSelectOfTwoConstants(). The fact that we see any x86
changes just shows that that code is a mess of special-case holes. We may be able to remove
some of that logic now.
My guess is that other targets will want to enable this hook for most cases. The likely
follow-ups would be to add value type and/or the constants themselves as parameters for the
hook. As the tests in select_const.ll show, we can transform any select-of-constants to
math/logic, but the general transform for any 2 constants needs one more instruction
(multiply or 'and').
ARM is one target that I think may not want this for most cases. I see infinite loops there
because it wants to use selects to enable conditionally executed instructions.
Differential Revision: https://reviews.llvm.org/D30537
llvm-svn: 296977
2017-03-05 03:18:09 +08:00
|
|
|
; CHECK-NEXT: movl $42, %eax
|
2017-09-19 06:05:35 +08:00
|
|
|
; CHECK-NEXT: subl %edi, %eax
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 41, i32 42
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @select_C_Cplus1_signext(i1 signext %cond) {
|
|
|
|
; CHECK-LABEL: select_C_Cplus1_signext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-10-09 23:22:20 +08:00
|
|
|
; CHECK-NEXT: andl $1, %edi
|
[DAGCombiner] allow transforming (select Cond, C +/- 1, C) to (add(ext Cond), C)
select Cond, C +/- 1, C --> add(ext Cond), C -- with a target hook.
This is part of the ongoing process to obsolete D24480. The motivation is to
canonicalize to select IR in InstCombine whenever possible, so we need to have a way to
undo that easily in codegen.
PowerPC is an obvious winner for this kind of transform because it has fast and complete
bit-twiddling abilities but generally lousy conditional execution perf (although this might
have changed in recent implementations).
x86 also sees some wins, but the effect is limited because these transforms already mostly
exist in its target-specific combineSelectOfTwoConstants(). The fact that we see any x86
changes just shows that that code is a mess of special-case holes. We may be able to remove
some of that logic now.
My guess is that other targets will want to enable this hook for most cases. The likely
follow-ups would be to add value type and/or the constants themselves as parameters for the
hook. As the tests in select_const.ll show, we can transform any select-of-constants to
math/logic, but the general transform for any 2 constants needs one more instruction
(multiply or 'and').
ARM is one target that I think may not want this for most cases. I see infinite loops there
because it wants to use selects to enable conditionally executed instructions.
Differential Revision: https://reviews.llvm.org/D30537
llvm-svn: 296977
2017-03-05 03:18:09 +08:00
|
|
|
; CHECK-NEXT: movl $42, %eax
|
2017-10-09 23:22:20 +08:00
|
|
|
; CHECK-NEXT: subl %edi, %eax
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 41, i32 42
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
2017-07-13 06:42:39 +08:00
|
|
|
; If the constants differ by a small multiplier, use LEA.
|
|
|
|
; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> LEA C2(Cond * (C1-C2))
|
|
|
|
|
|
|
|
define i32 @select_lea_2(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_lea_2:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: xorb $1, %dil
|
|
|
|
; CHECK-NEXT: movzbl %dil, %eax
|
|
|
|
; CHECK-NEXT: leal -1(%rax,%rax), %eax
|
2017-07-13 06:42:39 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 -1, i32 1
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @select_lea_3(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_lea_3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: xorb $1, %dil
|
|
|
|
; CHECK-NEXT: movzbl %dil, %eax
|
|
|
|
; CHECK-NEXT: leaq -2(%rax,%rax,2), %rax
|
2017-07-13 06:42:39 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i64 -2, i64 1
|
|
|
|
ret i64 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @select_lea_5(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_lea_5:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: xorb $1, %dil
|
|
|
|
; CHECK-NEXT: movzbl %dil, %eax
|
|
|
|
; CHECK-NEXT: leal -2(%rax,%rax,4), %eax
|
2017-07-13 06:42:39 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 -2, i32 3
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @select_lea_9(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_lea_9:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: xorb $1, %dil
|
|
|
|
; CHECK-NEXT: movzbl %dil, %eax
|
|
|
|
; CHECK-NEXT: leaq -7(%rax,%rax,8), %rax
|
2017-07-13 06:42:39 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i64 -7, i64 2
|
|
|
|
ret i64 %sel
|
|
|
|
}
|
|
|
|
|
2017-08-09 23:57:02 +08:00
|
|
|
; Should this be 'sbb x,x' or 'sbb 0,x' with simpler LEA or add?
|
|
|
|
|
|
|
|
define i64 @sel_1_2(i64 %x, i64 %y) {
|
|
|
|
; CHECK-LABEL: sel_1_2:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: cmpq $42, %rdi
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: sbbq $0, %rsi
|
|
|
|
; CHECK-NEXT: leaq 2(%rsi), %rax
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%cmp = icmp ult i64 %x, 42
|
|
|
|
%sel = select i1 %cmp, i64 1, i64 2
|
|
|
|
%sub = add i64 %sel, %y
|
|
|
|
ret i64 %sub
|
|
|
|
}
|
|
|
|
|
2017-08-11 23:44:14 +08:00
|
|
|
; No LEA with 8-bit, but this shouldn't need branches or cmov.
|
2017-08-09 23:57:02 +08:00
|
|
|
|
|
|
|
define i8 @sel_1_neg1(i32 %x) {
|
|
|
|
; CHECK-LABEL: sel_1_neg1:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: cmpl $42, %edi
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: setg %al
|
|
|
|
; CHECK-NEXT: shlb $2, %al
|
|
|
|
; CHECK-NEXT: decb %al
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%cmp = icmp sgt i32 %x, 42
|
|
|
|
%sel = select i1 %cmp, i8 3, i8 -1
|
|
|
|
ret i8 %sel
|
|
|
|
}
|
|
|
|
|
2017-08-11 23:44:14 +08:00
|
|
|
; We get an LEA for 16-bit because we ignore the high-bits.
|
|
|
|
|
2017-08-09 23:57:02 +08:00
|
|
|
define i16 @sel_neg1_1(i32 %x) {
|
|
|
|
; CHECK-LABEL: sel_neg1_1:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: xorl %eax, %eax
|
|
|
|
; CHECK-NEXT: cmpl $43, %edi
|
|
|
|
; CHECK-NEXT: setl %al
|
|
|
|
; CHECK-NEXT: leal -1(,%rax,4), %eax
|
2018-02-01 06:04:26 +08:00
|
|
|
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%cmp = icmp sgt i32 %x, 42
|
|
|
|
%sel = select i1 %cmp, i16 -1, i16 3
|
|
|
|
ret i16 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
; If the comparison is available, the predicate can be inverted.
|
|
|
|
|
|
|
|
define i32 @sel_1_neg1_32(i32 %x) {
|
|
|
|
; CHECK-LABEL: sel_1_neg1_32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: xorl %eax, %eax
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: cmpl $42, %edi
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: setg %al
|
|
|
|
; CHECK-NEXT: leal -1(%rax,%rax,8), %eax
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%cmp = icmp sgt i32 %x, 42
|
|
|
|
%sel = select i1 %cmp, i32 8, i32 -1
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @sel_neg1_1_32(i32 %x) {
|
|
|
|
; CHECK-LABEL: sel_neg1_1_32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: xorl %eax, %eax
|
|
|
|
; CHECK-NEXT: cmpl $43, %edi
|
|
|
|
; CHECK-NEXT: setl %al
|
|
|
|
; CHECK-NEXT: leal -7(%rax,%rax,8), %eax
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%cmp = icmp sgt i32 %x, 42
|
|
|
|
%sel = select i1 %cmp, i32 -7, i32 2
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
2017-07-13 06:42:39 +08:00
|
|
|
|
|
|
|
; If the constants differ by a large power-of-2, that can be a shift of the difference plus the smaller constant.
|
|
|
|
; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2
|
|
|
|
|
|
|
|
define i8 @select_pow2_diff(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_pow2_diff:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-NEXT: shlb $4, %al
|
|
|
|
; CHECK-NEXT: orb $3, %al
|
|
|
|
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
2017-07-13 06:42:39 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i8 19, i8 3
|
|
|
|
ret i8 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i16 @select_pow2_diff_invert(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_pow2_diff_invert:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: xorb $1, %dil
|
|
|
|
; CHECK-NEXT: movzbl %dil, %eax
|
|
|
|
; CHECK-NEXT: shll $6, %eax
|
|
|
|
; CHECK-NEXT: orl $7, %eax
|
2018-02-01 06:04:26 +08:00
|
|
|
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
|
2017-07-13 06:42:39 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i16 7, i16 71
|
|
|
|
ret i16 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @select_pow2_diff_neg(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_pow2_diff_neg:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: shlb $4, %dil
|
|
|
|
; CHECK-NEXT: movzbl %dil, %eax
|
|
|
|
; CHECK-NEXT: orl $-25, %eax
|
2017-07-13 06:42:39 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 -9, i32 -25
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @select_pow2_diff_neg_invert(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_pow2_diff_neg_invert:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-11 23:44:14 +08:00
|
|
|
; CHECK-NEXT: xorb $1, %dil
|
|
|
|
; CHECK-NEXT: movzbl %dil, %eax
|
|
|
|
; CHECK-NEXT: shlq $7, %rax
|
|
|
|
; CHECK-NEXT: addq $-99, %rax
|
2017-07-13 06:42:39 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i64 -99, i64 29
|
|
|
|
ret i64 %sel
|
|
|
|
}
|
|
|
|
|
2017-08-09 23:57:02 +08:00
|
|
|
; This doesn't need a branch, but don't do the wrong thing if subtraction of the constants overflows.
|
|
|
|
|
|
|
|
define i8 @sel_67_neg125(i32 %x) {
|
|
|
|
; CHECK-LABEL: sel_67_neg125:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: cmpl $42, %edi
|
|
|
|
; CHECK-NEXT: movb $67, %al
|
|
|
|
; CHECK-NEXT: jg .LBB31_2
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK-NEXT: # %bb.1:
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: movb $-125, %al
|
|
|
|
; CHECK-NEXT: .LBB31_2:
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%cmp = icmp sgt i32 %x, 42
|
|
|
|
%sel = select i1 %cmp, i8 67, i8 -125
|
|
|
|
ret i8 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2017-02-17 02:15:16 +08:00
|
|
|
; In general, select of 2 constants could be:
|
|
|
|
; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2
|
|
|
|
|
|
|
|
define i32 @select_C1_C2(i1 %cond) {
|
|
|
|
; CHECK-LABEL: select_C1_C2:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: testb $1, %dil
|
|
|
|
; CHECK-NEXT: movl $421, %ecx # imm = 0x1A5
|
|
|
|
; CHECK-NEXT: movl $42, %eax
|
|
|
|
; CHECK-NEXT: cmovnel %ecx, %eax
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 421, i32 42
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
|
|
|
|
; CHECK-LABEL: select_C1_C2_zeroext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-09-19 06:05:35 +08:00
|
|
|
; CHECK-NEXT: testl %edi, %edi
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: movl $421, %ecx # imm = 0x1A5
|
|
|
|
; CHECK-NEXT: movl $42, %eax
|
|
|
|
; CHECK-NEXT: cmovnel %ecx, %eax
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 421, i32 42
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @select_C1_C2_signext(i1 signext %cond) {
|
|
|
|
; CHECK-LABEL: select_C1_C2_signext:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-02-17 02:15:16 +08:00
|
|
|
; CHECK-NEXT: testb $1, %dil
|
|
|
|
; CHECK-NEXT: movl $421, %ecx # imm = 0x1A5
|
|
|
|
; CHECK-NEXT: movl $42, %eax
|
|
|
|
; CHECK-NEXT: cmovnel %ecx, %eax
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, i32 421, i32 42
|
|
|
|
ret i32 %sel
|
|
|
|
}
|
|
|
|
|
|
|
|
; select (x == 2), 2, (x + 1) --> select (x == 2), x, (x + 1)
|
|
|
|
|
2016-10-24 23:43:40 +08:00
|
|
|
define i64 @select_2_or_inc(i64 %x) {
|
|
|
|
; CHECK-LABEL: select_2_or_inc:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2016-10-24 23:43:40 +08:00
|
|
|
; CHECK-NEXT: leaq 1(%rdi), %rax
|
|
|
|
; CHECK-NEXT: cmpq $2, %rdi
|
|
|
|
; CHECK-NEXT: cmoveq %rdi, %rax
|
|
|
|
; CHECK-NEXT: retq
|
Reapply r165661, Patch by Shuxin Yang <shuxin.llvm@gmail.com>.
Original message:
The attached is the fix to radar://11663049. The optimization can be outlined by following rules:
(select (x != c), e, c) -> select (x != c), e, x),
(select (x == c), c, e) -> select (x == c), x, e)
where the <c> is an integer constant.
The reason for this change is that : on x86, conditional-move-from-constant needs two instructions;
however, conditional-move-from-register need only one instruction.
While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase.
The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource".
Original message since r165661:
My previous change has a bug: I negated the condition code of a CMOV, and go ahead creating a new CMOV using the *ORIGINAL* condition code.
llvm-svn: 166017
2012-10-16 14:28:34 +08:00
|
|
|
%cmp = icmp eq i64 %x, 2
|
|
|
|
%add = add i64 %x, 1
|
|
|
|
%retval.0 = select i1 %cmp, i64 2, i64 %add
|
|
|
|
ret i64 %retval.0
|
|
|
|
}
|
2016-10-24 23:43:40 +08:00
|
|
|
|
2017-03-02 04:31:23 +08:00
|
|
|
define <4 x i32> @sel_constants_add_constant_vec(i1 %cond) {
|
|
|
|
; CHECK-LABEL: sel_constants_add_constant_vec:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-03-02 04:31:23 +08:00
|
|
|
; CHECK-NEXT: testb $1, %dil
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: jne .LBB36_1
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK-NEXT: # %bb.2:
|
2017-03-02 06:51:31 +08:00
|
|
|
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [12,13,14,15]
|
2017-03-02 04:31:23 +08:00
|
|
|
; CHECK-NEXT: retq
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: .LBB36_1:
|
2017-03-02 06:51:31 +08:00
|
|
|
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [4294967293,14,4,4]
|
2017-03-02 04:31:23 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, <4 x i32> <i32 -4, i32 12, i32 1, i32 0>, <4 x i32> <i32 11, i32 11, i32 11, i32 11>
|
|
|
|
%bo = add <4 x i32> %sel, <i32 1, i32 2, i32 3, i32 4>
|
|
|
|
ret <4 x i32> %bo
|
|
|
|
}
|
|
|
|
|
|
|
|
define <2 x double> @sel_constants_fmul_constant_vec(i1 %cond) {
|
|
|
|
; CHECK-LABEL: sel_constants_fmul_constant_vec:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2017-03-02 04:31:23 +08:00
|
|
|
; CHECK-NEXT: testb $1, %dil
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: jne .LBB37_1
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK-NEXT: # %bb.2:
|
2018-10-29 12:52:04 +08:00
|
|
|
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1.1883E+2,3.4539999999999999E+1]
|
2017-03-02 04:31:23 +08:00
|
|
|
; CHECK-NEXT: retq
|
2017-08-09 23:57:02 +08:00
|
|
|
; CHECK-NEXT: .LBB37_1:
|
2018-10-29 12:52:04 +08:00
|
|
|
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [-2.0399999999999999E+1,3.768E+1]
|
2017-03-02 04:31:23 +08:00
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%sel = select i1 %cond, <2 x double> <double -4.0, double 12.0>, <2 x double> <double 23.3, double 11.0>
|
|
|
|
%bo = fmul <2 x double> %sel, <double 5.1, double 3.14>
|
|
|
|
ret <2 x double> %bo
|
|
|
|
}
|
2017-03-03 01:18:56 +08:00
|
|
|
|
|
|
|
; 4294967297 = 0x100000001.
|
|
|
|
; This becomes an opaque constant via ConstantHoisting, so we don't fold it into the select.
|
|
|
|
|
|
|
|
define i64 @opaque_constant(i1 %cond, i64 %x) {
|
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; CHECK-LABEL: opaque_constant:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0:
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2017-03-03 01:18:56 +08:00
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; CHECK-NEXT: testb $1, %dil
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2018-08-11 13:33:00 +08:00
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; CHECK-NEXT: movq $-4, %rcx
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; CHECK-NEXT: movl $23, %eax
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; CHECK-NEXT: cmovneq %rcx, %rax
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2017-03-03 01:18:56 +08:00
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; CHECK-NEXT: movabsq $4294967297, %rcx # imm = 0x100000001
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; CHECK-NEXT: andq %rcx, %rax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: cmpq %rcx, %rsi
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; CHECK-NEXT: sete %dl
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; CHECK-NEXT: subq %rdx, %rax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i64 -4, i64 23
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%bo = and i64 %sel, 4294967297
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%cmp = icmp eq i64 %x, 4294967297
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%sext = sext i1 %cmp to i64
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%add = add i64 %bo, %sext
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ret i64 %add
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}
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2018-11-19 22:39:57 +08:00
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define float @select_undef_fp(float %x) {
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; CHECK-LABEL: select_undef_fp:
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; CHECK: # %bb.0:
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2018-11-19 22:42:28 +08:00
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; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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2018-11-19 22:39:57 +08:00
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; CHECK-NEXT: retq
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%f = select i1 undef, float 4.0, float %x
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ret float %f
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}
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