maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll

75 lines
2.0 KiB
LLVM
Raw Normal View History

[ARM] Replace HasT2ExtractPack with HasDSP Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
2017-02-17 23:42:44 +08:00
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s %s -o - | FileCheck %s --check-prefix=CHECK-DSP
; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=CHECK-NO-DSP
; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-DSP
; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-NO-DSP
; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-DSP
Add thumb2 sign / zero extend with rotate instructions. llvm-svn: 74755
2009-07-03 09:43:10 +08:00
define i32 @test0(i8 %A) {
ARM: add patterns for [su]xta[bh] from just a shift. Although the final shifter operand is a rotate, this actually only matters for the half-word extends when the amount == 24. Otherwise folding a shift in is just as good. llvm-svn: 213753
2014-07-23 21:59:07 +08:00
; CHECK-LABEL: test0:
[ARM] Replace HasT2ExtractPack with HasDSP Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
2017-02-17 23:42:44 +08:00
; CHECK-DSP: sxtb r0, r0
; CHECK-NO-DSP: sxtb r0, r0
Add thumb2 sign / zero extend with rotate instructions. llvm-svn: 74755
2009-07-03 09:43:10 +08:00
%B = sext i8 %A to i32
ret i32 %B
}
manually upgrade a bunch of tests to modern syntax, and remove some that are either unreduced or only test old syntax. llvm-svn: 133228
2011-06-17 11:14:27 +08:00
define signext i8 @test1(i32 %A) {
ARM: add patterns for [su]xta[bh] from just a shift. Although the final shifter operand is a rotate, this actually only matters for the half-word extends when the amount == 24. Otherwise folding a shift in is just as good. llvm-svn: 213753
2014-07-23 21:59:07 +08:00
; CHECK-LABEL: test1:
[ARM] Replace HasT2ExtractPack with HasDSP Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
2017-02-17 23:42:44 +08:00
; CHECK-DSP: sbfx r0, r0, #8, #8
; CHECK-NO-DSP: sbfx r0, r0, #8, #8
Add thumb2 sign / zero extend with rotate instructions. llvm-svn: 74755
2009-07-03 09:43:10 +08:00
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
%E = trunc i32 %D to i8
ret i8 %E
}
manually upgrade a bunch of tests to modern syntax, and remove some that are either unreduced or only test old syntax. llvm-svn: 133228
2011-06-17 11:14:27 +08:00
define signext i32 @test2(i32 %A, i32 %X) {
ARM: add patterns for [su]xta[bh] from just a shift. Although the final shifter operand is a rotate, this actually only matters for the half-word extends when the amount == 24. Otherwise folding a shift in is just as good. llvm-svn: 213753
2014-07-23 21:59:07 +08:00
; CHECK-LABEL: test2:
[ARM] Replace HasT2ExtractPack with HasDSP Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
2017-02-17 23:42:44 +08:00
; CHECK-DSP: sxtab r0, r1, r0, ror #8
; CHECK-NO-DSP-NOT: sxtab
Add thumb2 sign / zero extend with rotate instructions. llvm-svn: 74755
2009-07-03 09:43:10 +08:00
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
%E = trunc i32 %D to i8
%F = sext i8 %E to i32
%G = add i32 %F, %X
ret i32 %G
}
ARM: add patterns for [su]xta[bh] from just a shift. Although the final shifter operand is a rotate, this actually only matters for the half-word extends when the amount == 24. Otherwise folding a shift in is just as good. llvm-svn: 213753
2014-07-23 21:59:07 +08:00
define i32 @test3(i32 %A, i32 %X) {
; CHECK-LABEL: test3:
[ARM] Replace HasT2ExtractPack with HasDSP Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
2017-02-17 23:42:44 +08:00
; CHECK-DSP: sxtah r0, r0, r1, ror #8
; CHECK-NO-DSP-NOT: sxtah
ARM: add patterns for [su]xta[bh] from just a shift. Although the final shifter operand is a rotate, this actually only matters for the half-word extends when the amount == 24. Otherwise folding a shift in is just as good. llvm-svn: 213753
2014-07-23 21:59:07 +08:00
%X.hi = lshr i32 %X, 8
%X.trunc = trunc i32 %X.hi to i16
%addend = sext i16 %X.trunc to i32
%sum = add i32 %A, %addend
ret i32 %sum
}
[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 17:34:34 +08:00
define signext i32 @test4(i32 %A, i32 %X) {
; CHECK-LABEL: test4:
[ARM] Replace HasT2ExtractPack with HasDSP Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
2017-02-17 23:42:44 +08:00
; CHECK-DSP: sxtab r0, r1, r0, ror #16
; CHECK-NO-DSP-NOT: sxtab
[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 17:34:34 +08:00
%B = lshr i32 %A, 16
%C = shl i32 %A, 16
%D = or i32 %B, %C
%E = trunc i32 %D to i8
%F = sext i8 %E to i32
%G = add i32 %F, %X
ret i32 %G
}
define signext i32 @test5(i32 %A, i32 %X) {
; CHECK-LABEL: test5:
[ARM] Replace HasT2ExtractPack with HasDSP Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
2017-02-17 23:42:44 +08:00
; CHECK-DSP: sxtah r0, r1, r0, ror #24
; CHECK-NO-DSP-NOT: sxtah
[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 17:34:34 +08:00
%B = lshr i32 %A, 24
%C = shl i32 %A, 8
%D = or i32 %B, %C
%E = trunc i32 %D to i16
%F = sext i16 %E to i32
%G = add i32 %F, %X
ret i32 %G
}