llvm-project/llvm/lib/Target/AMDGPU/CMakeLists.txt

set(LLVM_TARGET_DEFINITIONS AMDGPU.td)

tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
add_public_tablegen_target(AMDGPUCommonTableGen)

add_llvm_target(AMDGPUCodeGen
  AMDILCFGStructurizer.cpp
  AMDGPUAlwaysInlinePass.cpp
  AMDGPUAnnotateKernelFeatures.cpp
  AMDGPUAnnotateUniformValues.cpp
  AMDGPUAsmPrinter.cpp
  AMDGPUDiagnosticInfoUnsupported.cpp
  AMDGPUFrameLowering.cpp
  AMDGPUTargetObjectFile.cpp
  AMDGPUIntrinsicInfo.cpp
  AMDGPUISelDAGToDAG.cpp
  AMDGPUMCInstLower.cpp
  AMDGPUMachineFunction.cpp
  AMDGPUOpenCLImageTypeLoweringPass.cpp
  AMDGPUSubtarget.cpp
  AMDGPUTargetMachine.cpp
  AMDGPUTargetTransformInfo.cpp
  AMDGPUISelLowering.cpp
  AMDGPUInstrInfo.cpp
  AMDGPUPromoteAlloca.cpp
  AMDGPURegisterInfo.cpp
  R600ClauseMergePass.cpp
  R600ControlFlowFinalizer.cpp
  R600EmitClauseMarkers.cpp
  R600ExpandSpecialInstrs.cpp
  R600InstrInfo.cpp
  R600ISelLowering.cpp
  R600MachineFunctionInfo.cpp
  R600MachineScheduler.cpp
  R600OptimizeVectorRegisters.cpp
  R600Packetizer.cpp
  R600RegisterInfo.cpp
  R600TextureIntrinsicsReplacer.cpp
  SIAnnotateControlFlow.cpp
  SIFixControlFlowLiveIntervals.cpp
  SIFixSGPRCopies.cpp
  SIFixSGPRLiveRanges.cpp
  SIFoldOperands.cpp
  SIFrameLowering.cpp
  SIInsertWaits.cpp
  SIInstrInfo.cpp
  SIISelLowering.cpp
  SILoadStoreOptimizer.cpp
  SILowerControlFlow.cpp
  SILowerI1Copies.cpp
  SIMachineFunctionInfo.cpp
  SIRegisterInfo.cpp
  SIShrinkInstructions.cpp
  SITypeRewriter.cpp
  )

add_subdirectory(AsmParser)
add_subdirectory(InstPrinter)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)
add_subdirectory(Utils)
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`set(LLVM_TARGET_DEFINITIONS AMDGPU.td)`

			`tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)`
			`tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)`
			`tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)`
			`tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)`
			`tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)`
			`tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)`
Reinstate "Nuke the old JIT." Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982 2014-09-03 06:28:02 +08:00			`tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)`
			`tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)`
R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994 2014-11-14 22:08:00 +08:00			`tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`add_public_tablegen_target(AMDGPUCommonTableGen)`

R600 -> AMDGPU rename llvm-svn: 239657 2015-06-13 11:28:10 +08:00			`add_llvm_target(AMDGPUCodeGen`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`AMDILCFGStructurizer.cpp`
Reapply: R600: Make sure to inline all internal functions Function calls aren't supported yet. This was reverted due to build breakages, which should be fixed now. llvm-svn: 221173 2014-11-04 03:49:05 +08:00			`AMDGPUAlwaysInlinePass.cpp`
AMDGPU: Add pass to detect used kernel features Mark kernels that use certain features that require user SGPRs to support with kernel attributes. We need to know before instruction selection begins because it impacts the kernel calling convention lowering. For now this only detects the workitem intrinsics. llvm-svn: 252323 2015-11-07 02:01:57 +08:00			`AMDGPUAnnotateKernelFeatures.cpp`
AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions Summary: We were previously selecting all constant loads to SMRD instructions and legalizing the SMRDs with non-uniform addresses during the SIFixSGPRCopesPass. This new solution is more simple and also generates much better code, because the instruction selector is able to take advantage of all the MUBUF addressing modes that are legalization pass wasn't able to. We also no longer need to generate v_add_* instructions when we have a uniform pointer and a non-uniform offset, as this is now folded into the MUBUF instruction during instruction selection. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15425 llvm-svn: 255672 2015-12-16 04:55:55 +08:00			`AMDGPUAnnotateUniformValues.cpp`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`AMDGPUAsmPrinter.cpp`
AMDGPU: Split DiagnosticInfoUnsupported into its own file llvm-svn: 250959 2015-10-22 06:37:46 +08:00			`AMDGPUDiagnosticInfoUnsupported.cpp`
R600: Support for indirect addressing v4 Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525 2013-02-07 01:32:29 +08:00			`AMDGPUFrameLowering.cpp`
AMDGPU/SI: Emit constant arrays in the .text section Summary: This allows us to remove the END_OF_TEXT_LABEL hack we had been using and simplifies the fixups used to compute the address of constant arrays. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15257 llvm-svn: 255204 2015-12-10 10:13:01 +08:00			`AMDGPUTargetObjectFile.cpp`
R600: Rename AMDIL file llvm-svn: 211512 2014-06-24 02:00:31 +08:00			`AMDGPUIntrinsicInfo.cpp`
R600: Rename AMDILISelDAGToDAG.cpp -> AMDGPUISelDAGToDAG.cpp Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186920 2013-07-23 09:48:29 +08:00			`AMDGPUISelDAGToDAG.cpp`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`AMDGPUMCInstLower.cpp`
Target/R600: Fix CMake build to add missing files. llvm-svn: 178508 2013-04-02 06:05:58 +08:00			`AMDGPUMachineFunction.cpp`
AMDGPU: Add pass to lower OpenCL image and sampler arguments. The pass adds new kernel arguments for image attributes, and resolves calls to dummy attribute and resource id getter functions. Patch by: Zoltan Gilian llvm-svn: 244372 2015-08-08 07:19:30 +08:00			`AMDGPUOpenCLImageTypeLoweringPass.cpp`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`AMDGPUSubtarget.cpp`
			`AMDGPUTargetMachine.cpp`
SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions Merge consecutive if-regions if they contain identical statements. Both transformations reduce number of branches. The transformation is guarded by a target-hook, and is currently enabled only for +R600, but the correctness has been tested on X86 target using a variety of CPU benchmarks. Patch by: Mei Ye llvm-svn: 187278 2013-07-27 08:01:07 +08:00			`AMDGPUTargetTransformInfo.cpp`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`AMDGPUISelLowering.cpp`
			`AMDGPUInstrInfo.cpp`
R600: Use LDS and vectors for private memory llvm-svn: 211110 2014-06-18 00:53:14 +08:00			`AMDGPUPromoteAlloca.cpp`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`AMDGPURegisterInfo.cpp`
R600: add a pass that merges clauses. llvm-svn: 191790 2013-10-02 03:32:58 +08:00			`R600ClauseMergePass.cpp`
Target/R600: Fix CMake build to add missing files. llvm-svn: 178508 2013-04-02 06:05:58 +08:00			`R600ControlFlowFinalizer.cpp`
			`R600EmitClauseMarkers.cpp`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`R600ExpandSpecialInstrs.cpp`
			`R600InstrInfo.cpp`
			`R600ISelLowering.cpp`
			`R600MachineFunctionInfo.cpp`
Update cmake build. llvm-svn: 176501 2013-03-06 02:54:05 +08:00			`R600MachineScheduler.cpp`
R600: Add a pass that merge Vector Register Previously commited @183279 but tests were failing, reverted @183286 It was broken because @183336 was missing, now it's there. llvm-svn: 183343 2013-06-06 05:38:04 +08:00			`R600OptimizeVectorRegisters.cpp`
R600: Packetize instructions llvm-svn: 180760 2013-04-30 08:14:27 +08:00			`R600Packetizer.cpp`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`R600RegisterInfo.cpp`
R600: Improve texture handling llvm-svn: 182125 2013-05-18 00:50:20 +08:00			`R600TextureIntrinsicsReplacer.cpp`
R600: New control flow for SI v2 This patch replaces the control flow handling with a new pass which structurize the graph before transforming it to machine instruction. This has a couple of different advantages and currently fixes 20 piglit tests without a single regression. It is now a general purpose transformation that could be not only be used for SI/R6xx, but also for other hardware implementations that use a form of structurized control flow. v2: further cleanup, fixes and documentation Patch by: Christian König Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 170591 2012-12-20 06:10:31 +08:00			`SIAnnotateControlFlow.cpp`
R600/SI: add pass to mark CF live ranges as non-spillable Spilling can insert instructions almost anywhere, and this can mess up control flow lowering in a multitude of ways, due to instruction reordering. Let's sort this out the easy way: never spill registers involved with control flow, i.e. saved EXEC masks. Unfortunately, this does not work at all with optimizations disabled, as the register allocator ignores spill weights. This should be addressed in a future commit. The test was reduced from the "stacks" shader of [1]. Some issues trigger the machine verifier while another one is checked manually. [1] http://madebyevan.com/webgl-path-tracing/ v2: only insert pass with optimizations enabled, merge test runs. Patch by: Grigori Goronzy llvm-svn: 237152 2015-05-13 01:13:02 +08:00			`SIFixControlFlowLiveIntervals.cpp`
R600: Add new file from r187831 to CMakeLists.txt llvm-svn: 187834 2013-08-07 07:12:34 +08:00			`SIFixSGPRCopies.cpp`
R600/SI: Adjsut SGPR live ranges before register allocation SGPRs are written by instructions that sometimes will ignore control flow, which means if you have code like: if (VGPR0) { SGPR0 = S_MOV_B32 0 } else { SGPR0 = S_MOV_B32 1 } The value of SGPR0 will 1 no matter what the condition is. In order to deal with this situation correctly, we need to view the program as if it were a single basic block when we calculate the live ranges for the SGPRs. They way we actually update the live range is by iterating over all of the segments in each LiveRange object and setting the end of each segment equal to the start of the next segment. So a live range like: [3888r,9312r:0)[10032B,10384B:0) 0@3888r will become: [3888r,10032B:0)[10032B,10384B:0) 0@3888r This change will allow us to use SALU instructions within branches. llvm-svn: 212215 2014-07-03 04:53:48 +08:00			`SIFixSGPRLiveRanges.cpp`
R600/SI: Add SIFoldOperands pass This pass attempts to fold the source operands of mov and copy instructions into their uses. llvm-svn: 222581 2014-11-22 06:06:37 +08:00			`SIFoldOperands.cpp`
AMDGPU: Create emergency stack slots during frame lowering Test has a bogus verifier error which will be fixed by later commits. llvm-svn: 252327 2015-11-07 02:17:45 +08:00			`SIFrameLowering.cpp`
R600: Proper insert S_WAITCNT instructions Some instructions like memory reads/writes are executed asynchronously, so we need to insert S_WAITCNT instructions to block before accessing their results. Previously we have just inserted S_WAITCNT instructions after each async instruction, this patch fixes this and adds a prober insertion pass. Patch by: Christian König Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 172846 2013-01-19 05:15:53 +08:00			`SIInsertWaits.cpp`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`SIInstrInfo.cpp`
			`SIISelLowering.cpp`
R600/SI: Add load / store machine optimizer pass. Currently this only functions to match simple cases where ds_read2_* / ds_write2_* instructions can be used. In the future it might match some of the other weird load patterns, such as direct to LDS loads. Currently enabled only with a subtarget feature to enable easier testing. llvm-svn: 219533 2014-10-11 06:01:59 +08:00			`SILoadStoreOptimizer.cpp`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`SILowerControlFlow.cpp`
R600/SI: Use VALU instructions for copying i1 values We can't use SALU instructions for this since they ignore the EXEC mask and are always executed. This fixes several OpenCV tests. llvm-svn: 207661 2014-04-30 23:31:33 +08:00			`SILowerI1Copies.cpp`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`SIMachineFunctionInfo.cpp`
			`SIRegisterInfo.cpp`
R600/SI: Add instruction shrinking pass This pass converts 64-bit instructions to 32-bit when possible. llvm-svn: 213561 2014-07-22 00:55:33 +08:00			`SIShrinkInstructions.cpp`
R600/SI: Convert v16i8 resource descriptors to i128 Now that compute support is better on SI, we can't continue using v16i8 for descriptors since this is also a legal type in OpenCL. This patch fixes numerous hangs with the piglit OpenCL test and since we now use a target specific DAG node for LOAD_CONSTANT with the correct MemOperandFlags, this should also fix: https://bugs.freedesktop.org/show_bug.cgi?id=66805 llvm-svn: 188429 2013-08-15 07:24:45 +08:00			`SITypeRewriter.cpp`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`)`

R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994 2014-11-14 22:08:00 +08:00			`add_subdirectory(AsmParser)`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 2012-12-12 05:25:42 +08:00			`add_subdirectory(InstPrinter)`
			`add_subdirectory(TargetInfo)`
			`add_subdirectory(MCTargetDesc)`
AMDGPU/SI: Add hsa code object directives Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10757 llvm-svn: 240831 2015-06-27 05:15:07 +08:00			`add_subdirectory(Utils)`