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llvm-project/llvm/test/MC/AVR/inst-in.s

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[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
[AVR] Implement disassembly support for I/O instructions The in, out, and sbi/cbi family of instructions seem to require a custom decoder. I'm not exactly sure why and would prefer to convince TableGen to provide the correct decoders for these, but I can't seem to convince it to do so. They simply disassemble without any operands. Differential Revision: https://reviews.llvm.org/D74049
2020-02-05 22:04:47 +08:00
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
foo:
in r2, 4
in r9, 6
in r5, 32
in r0, 0
[AVR] Implement disassembly support for I/O instructions The in, out, and sbi/cbi family of instructions seem to require a custom decoder. I'm not exactly sure why and would prefer to convince TableGen to provide the correct decoders for these, but I can't seem to convince it to do so. They simply disassemble without any operands. Differential Revision: https://reviews.llvm.org/D74049
2020-02-05 22:04:47 +08:00
in r31, 0
in r0, 63
in r31, 63
[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
in r20, foo+1
; CHECK: in r2, 4 ; encoding: [0x24,0xb0]
; CHECK: in r9, 6 ; encoding: [0x96,0xb0]
; CHECK: in r5, 32 ; encoding: [0x50,0xb4]
; CHECK: in r0, 0 ; encoding: [0x00,0xb0]
[AVR] Implement disassembly support for I/O instructions The in, out, and sbi/cbi family of instructions seem to require a custom decoder. I'm not exactly sure why and would prefer to convince TableGen to provide the correct decoders for these, but I can't seem to convince it to do so. They simply disassemble without any operands. Differential Revision: https://reviews.llvm.org/D74049
2020-02-05 22:04:47 +08:00
; CHECK: in r31, 0 ; encoding: [0xf0,0xb1]
; CHECK: in r0, 63 ; encoding: [0x0f,0xb6]
; CHECK: in r31, 63 ; encoding: [0xff,0xb7]
[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
; CHECK: in r20, foo+1 ; encoding: [0x40'A',0xb1'A']
; CHECK: ; fixup A - offset: 0, value: foo+1, kind: fixup_port6
[AVR] Implement disassembly support for I/O instructions The in, out, and sbi/cbi family of instructions seem to require a custom decoder. I'm not exactly sure why and would prefer to convince TableGen to provide the correct decoders for these, but I can't seem to convince it to do so. They simply disassemble without any operands. Differential Revision: https://reviews.llvm.org/D74049
2020-02-05 22:04:47 +08:00
; CHECK-INST: in r2, 4
; CHECK-INST: in r9, 6
; CHECK-INST: in r5, 32
; CHECK-INST: in r0, 0
; CHECK-INST: in r31, 0
; CHECK-INST: in r0, 63
; CHECK-INST: in r31, 63
; CHECK-INST: in r20, 0