forked from OSchip/llvm-project
16 lines
532 B
LLVM
16 lines
532 B
LLVM
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; RUN: llc -O2 -mcpu=hexagonv5 < %s | FileCheck %s
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; There should be no register pair used.
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; CHECK-NOT: r{{.*}}:{{[0-9]}} = and
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; CHECK-NOT: r{{.*}}:{{[0-9]}} = xor
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target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
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target triple = "hexagon"
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define i32 @foo(i64 %x, i64 %y, i64 %z) nounwind readnone {
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entry:
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%and = and i64 %y, -361700868401135616
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%xor = xor i64 %and, %z
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%shr1 = lshr i64 %xor, 32
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%conv = trunc i64 %shr1 to i32
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ret i32 %conv
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}
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