2017-08-07 22:58:04 +08:00
|
|
|
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
2017-01-25 06:02:15 +08:00
|
|
|
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
2016-11-13 15:01:11 +08:00
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}fadd_f16
|
2017-07-05 01:32:00 +08:00
|
|
|
; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]
|
|
|
|
|
; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
|
2016-11-13 15:01:11 +08:00
|
|
|
; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
|
|
|
|
|
; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
|
2017-07-11 03:53:57 +08:00
|
|
|
; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]
|
2016-11-13 15:01:11 +08:00
|
|
|
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
|
2017-07-11 03:53:57 +08:00
|
|
|
; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]]
|
2016-11-13 15:01:11 +08:00
|
|
|
; GCN: buffer_store_short v[[R_F16]]
|
|
|
|
|
; GCN: s_endpgm
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fadd_f16(
|
2016-11-13 15:01:11 +08:00
|
|
|
half addrspace(1)* %r,
|
|
|
|
|
half addrspace(1)* %a,
|
|
|
|
|
half addrspace(1)* %b) {
|
|
|
|
|
entry:
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
%a.val = load volatile half, half addrspace(1)* %a
|
|
|
|
|
%b.val = load volatile half, half addrspace(1)* %b
|
2016-11-13 15:01:11 +08:00
|
|
|
%r.val = fadd half %a.val, %b.val
|
|
|
|
|
store half %r.val, half addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}fadd_f16_imm_a
|
2017-07-05 01:32:00 +08:00
|
|
|
; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
|
2016-11-13 15:01:11 +08:00
|
|
|
; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
|
2017-01-31 00:57:41 +08:00
|
|
|
; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], 1.0, v[[B_F32]]
|
2016-11-13 15:01:11 +08:00
|
|
|
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], 1.0, v[[B_F16]]
|
2016-11-13 15:01:11 +08:00
|
|
|
; GCN: buffer_store_short v[[R_F16]]
|
|
|
|
|
; GCN: s_endpgm
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fadd_f16_imm_a(
|
2016-11-13 15:01:11 +08:00
|
|
|
half addrspace(1)* %r,
|
|
|
|
|
half addrspace(1)* %b) {
|
|
|
|
|
entry:
|
|
|
|
|
%b.val = load half, half addrspace(1)* %b
|
|
|
|
|
%r.val = fadd half 1.0, %b.val
|
|
|
|
|
store half %r.val, half addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}fadd_f16_imm_b
|
2017-07-05 01:32:00 +08:00
|
|
|
; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]
|
2016-11-13 15:01:11 +08:00
|
|
|
; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
|
2017-01-31 00:57:41 +08:00
|
|
|
; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], 2.0, v[[A_F32]]
|
2016-11-13 15:01:11 +08:00
|
|
|
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], 2.0, v[[A_F16]]
|
2016-11-13 15:01:11 +08:00
|
|
|
; GCN: buffer_store_short v[[R_F16]]
|
|
|
|
|
; GCN: s_endpgm
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fadd_f16_imm_b(
|
2016-11-13 15:01:11 +08:00
|
|
|
half addrspace(1)* %r,
|
|
|
|
|
half addrspace(1)* %a) {
|
|
|
|
|
entry:
|
|
|
|
|
%a.val = load half, half addrspace(1)* %a
|
|
|
|
|
%r.val = fadd half %a.val, 2.0
|
|
|
|
|
store half %r.val, half addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-16 03:04:26 +08:00
|
|
|
; GCN-LABEL: {{^}}fadd_v2f16:
|
2017-09-14 06:20:47 +08:00
|
|
|
; SI: buffer_load_dword v[[A_V2_F16:[0-9]+]]
|
|
|
|
|
; SI: buffer_load_dword v[[B_V2_F16:[0-9]+]]
|
|
|
|
|
; VI: flat_load_dword v[[B_V2_F16:[0-9]+]]
|
|
|
|
|
; VI: flat_load_dword v[[A_V2_F16:[0-9]+]]
|
2017-03-16 03:04:26 +08:00
|
|
|
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
|
|
|
|
|
; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
|
|
|
|
|
; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]]
|
|
|
|
|
; SI-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
|
2017-03-16 03:04:26 +08:00
|
|
|
|
|
|
|
|
; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
|
|
|
|
|
; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]]
|
2017-07-11 03:53:57 +08:00
|
|
|
; SI-DAG: v_add_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]], v[[B_F32_0]]
|
|
|
|
|
; SI-DAG: v_add_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]], v[[B_F32_1]]
|
2017-03-16 03:04:26 +08:00
|
|
|
; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
|
|
|
|
|
; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
|
2017-04-06 23:03:28 +08:00
|
|
|
; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
|
2017-07-11 03:53:57 +08:00
|
|
|
; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
|
2017-04-06 23:03:28 +08:00
|
|
|
|
2017-07-11 03:53:57 +08:00
|
|
|
; VI-DAG: v_add_f16_e32 v[[R_F16_LO:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]]
|
2017-06-04 01:39:47 +08:00
|
|
|
; VI-DAG: v_add_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
2017-07-11 03:53:57 +08:00
|
|
|
; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_LO]], v[[R_F16_HI]]
|
2017-03-16 03:04:26 +08:00
|
|
|
|
2016-11-13 15:01:11 +08:00
|
|
|
; GCN: buffer_store_dword v[[R_V2_F16]]
|
|
|
|
|
; GCN: s_endpgm
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fadd_v2f16(
|
2016-11-13 15:01:11 +08:00
|
|
|
<2 x half> addrspace(1)* %r,
|
|
|
|
|
<2 x half> addrspace(1)* %a,
|
|
|
|
|
<2 x half> addrspace(1)* %b) {
|
|
|
|
|
entry:
|
2017-07-05 01:32:00 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
|
|
%gep.a = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %a, i32 %tid
|
|
|
|
|
%gep.b = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %b, i32 %tid
|
|
|
|
|
%a.val = load <2 x half>, <2 x half> addrspace(1)* %gep.a
|
|
|
|
|
%b.val = load <2 x half>, <2 x half> addrspace(1)* %gep.b
|
2016-11-13 15:01:11 +08:00
|
|
|
%r.val = fadd <2 x half> %a.val, %b.val
|
|
|
|
|
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-16 03:04:26 +08:00
|
|
|
; GCN-LABEL: {{^}}fadd_v2f16_imm_a:
|
2017-07-05 01:32:00 +08:00
|
|
|
; GCN-DAG: {{buffer|flat}}_load_dword v[[B_V2_F16:[0-9]+]]
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]]
|
|
|
|
|
; SI-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
|
|
|
|
|
; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]]
|
|
|
|
|
; SI-DAG: v_add_f32_e32 v[[R_F32_0:[0-9]+]], 1.0, v[[B_F32_0]]
|
|
|
|
|
; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
|
|
|
|
|
; SI-DAG: v_add_f32_e32 v[[R_F32_1:[0-9]+]], 2.0, v[[B_F32_1]]
|
|
|
|
|
; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
|
2017-04-06 23:03:28 +08:00
|
|
|
; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
|
2017-07-11 03:53:57 +08:00
|
|
|
; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
|
2017-04-06 23:03:28 +08:00
|
|
|
|
2017-05-31 00:49:24 +08:00
|
|
|
; VI-DAG: v_mov_b32_e32 v[[CONST2:[0-9]+]], 0x4000
|
2017-06-04 01:39:47 +08:00
|
|
|
; VI-DAG: v_add_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[B_V2_F16]], v[[CONST2]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
2017-04-06 23:03:28 +08:00
|
|
|
; VI-DAG: v_add_f16_e32 v[[R_F16_0:[0-9]+]], 1.0, v[[B_V2_F16]]
|
2017-07-11 03:53:57 +08:00
|
|
|
; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
|
2017-01-31 00:57:41 +08:00
|
|
|
|
2016-11-13 15:01:11 +08:00
|
|
|
; GCN: buffer_store_dword v[[R_V2_F16]]
|
|
|
|
|
; GCN: s_endpgm
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fadd_v2f16_imm_a(
|
2016-11-13 15:01:11 +08:00
|
|
|
<2 x half> addrspace(1)* %r,
|
|
|
|
|
<2 x half> addrspace(1)* %b) {
|
|
|
|
|
entry:
|
2017-07-05 01:32:00 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
|
|
%gep.b = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %b, i32 %tid
|
|
|
|
|
%b.val = load <2 x half>, <2 x half> addrspace(1)* %gep.b
|
2016-11-13 15:01:11 +08:00
|
|
|
%r.val = fadd <2 x half> <half 1.0, half 2.0>, %b.val
|
|
|
|
|
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-16 03:04:26 +08:00
|
|
|
; GCN-LABEL: {{^}}fadd_v2f16_imm_b:
|
2017-07-05 01:32:00 +08:00
|
|
|
; GCN-DAG: {{buffer|flat}}_load_dword v[[A_V2_F16:[0-9]+]]
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
|
2017-05-31 00:49:24 +08:00
|
|
|
; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
|
|
|
|
|
; SI-DAG: v_add_f32_e32 v[[R_F32_0:[0-9]+]], 2.0, v[[A_F32_0]]
|
|
|
|
|
; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
|
|
|
|
|
; SI-DAG: v_add_f32_e32 v[[R_F32_1:[0-9]+]], 1.0, v[[A_F32_1]]
|
|
|
|
|
; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
|
2017-04-06 23:03:28 +08:00
|
|
|
; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
|
2017-07-11 03:53:57 +08:00
|
|
|
; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
|
2017-04-06 23:03:28 +08:00
|
|
|
|
2017-05-31 00:49:24 +08:00
|
|
|
; VI-DAG: v_mov_b32_e32 v[[CONST1:[0-9]+]], 0x3c00
|
2017-06-04 01:39:47 +08:00
|
|
|
; VI-DAG: v_add_f16_sdwa v[[R_F16_0:[0-9]+]], v[[A_V2_F16]], v[[CONST1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
2017-04-06 23:03:28 +08:00
|
|
|
; VI-DAG: v_add_f16_e32 v[[R_F16_1:[0-9]+]], 2.0, v[[A_V2_F16]]
|
2017-07-11 03:53:57 +08:00
|
|
|
; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
|
2017-04-06 23:03:28 +08:00
|
|
|
|
2016-11-13 15:01:11 +08:00
|
|
|
; GCN: buffer_store_dword v[[R_V2_F16]]
|
|
|
|
|
; GCN: s_endpgm
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fadd_v2f16_imm_b(
|
2016-11-13 15:01:11 +08:00
|
|
|
<2 x half> addrspace(1)* %r,
|
|
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|
|
<2 x half> addrspace(1)* %a) {
|
|
|
|
|
entry:
|
2017-07-05 01:32:00 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
|
|
%gep.a = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %a, i32 %tid
|
|
|
|
|
%a.val = load <2 x half>, <2 x half> addrspace(1)* %gep.a
|
2016-11-13 15:01:11 +08:00
|
|
|
%r.val = fadd <2 x half> %a.val, <half 2.0, half 1.0>
|
|
|
|
|
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2017-07-05 01:32:00 +08:00
|
|
|
|
|
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
|
|
|
|
|
|
|
attributes #0 = { nounwind }
|
|
|
|
|
attributes #1 = { nounwind readnone }
|