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llvm-project/llvm/test/CodeGen/X86/avx512-build-vector.ll

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Make utils/update_llc_test_checks.py note that the assertions are autogenerated. Also update existing test cases which appear to be generated by it and weren't modified (other than addition of the header) by rerunning it. llvm-svn: 253917
2015-11-24 05:33:58 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
X86: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309774
2017-08-02 08:28:10 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectors llvm-svn: 189189
2013-08-25 20:54:30 +08:00
define <16 x i32> @test2(<16 x i32> %x) {
[x86] Regenerate a bunch more avx512 test cases using my script to have tighter, more strict FileCheck assertions. Some of these I really like as they show case exactly what instruction sequences come out of these microscopic functionality tests. llvm-svn: 218936
2014-10-03 08:50:03 +08:00
; CHECK-LABEL: test2:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
[AVX512] Use vpternlog with an immediate of 0xff to create 512-bit all one vectors. llvm-svn: 275045
2016-07-11 13:36:48 +08:00
; CHECK-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1
; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0
[x86] Regenerate a bunch more avx512 test cases using my script to have tighter, more strict FileCheck assertions. Some of these I really like as they show case exactly what instruction sequences come out of these microscopic functionality tests. llvm-svn: 218936
2014-10-03 08:50:03 +08:00
; CHECK-NEXT: retq
AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectors llvm-svn: 189189
2013-08-25 20:54:30 +08:00
%res = add <16 x i32><i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, %x
ret <16 x i32>%res
AVX-512: Optimized BUILD_VECTOR pattern; fixed encoding of VEXTRACTPS instruction. llvm-svn: 201134
2014-02-11 15:25:59 +08:00
}
define <16 x float> @test3(<4 x float> %a) {
[x86] Regenerate a bunch more avx512 test cases using my script to have tighter, more strict FileCheck assertions. Some of these I really like as they show case exactly what instruction sequences come out of these microscopic functionality tests. llvm-svn: 218936
2014-10-03 08:50:03 +08:00
; CHECK-LABEL: test3:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
[AVX-512] Correct execution domain for VPERMT2PS and VPERMI2PS. llvm-svn: 284328
2016-10-16 12:54:31 +08:00
; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [0,1,2,3,4,18,16,7,8,9,10,11,12,13,14,15]
[X86] SET0 to use XMM registers where possible PR26018 PR32862 Differential Revision: https://reviews.llvm.org/D35965 llvm-svn: 309926
2017-08-03 16:50:18 +08:00
; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
[DAGCombiner] Teach createBuildVecShuffle to handle cases where input vectors are less than half of the output vector size. This will be needed by a future commit to support sign/zero extending from v8i8 to v8i64 which requires a sign/zero_extend_vector_inreg to be created which requires v8i8 to be concatenated upto v64i8 and goes through this code. llvm-svn: 284204
2016-10-14 14:00:42 +08:00
; CHECK-NEXT: vpermt2ps %zmm0, %zmm2, %zmm1
[AVX-512] Correct execution domain for VPERMT2PS and VPERMI2PS. llvm-svn: 284328
2016-10-16 12:54:31 +08:00
; CHECK-NEXT: vmovaps %zmm1, %zmm0
[x86] Regenerate a bunch more avx512 test cases using my script to have tighter, more strict FileCheck assertions. Some of these I really like as they show case exactly what instruction sequences come out of these microscopic functionality tests. llvm-svn: 218936
2014-10-03 08:50:03 +08:00
; CHECK-NEXT: retq
AVX-512: Optimized BUILD_VECTOR pattern; fixed encoding of VEXTRACTPS instruction. llvm-svn: 201134
2014-02-11 15:25:59 +08:00
%b = extractelement <4 x float> %a, i32 2
%c = insertelement <16 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %b, i32 5
%b1 = extractelement <4 x float> %a, i32 0
%c1 = insertelement <16 x float> %c, float %b1, i32 6
ret <16 x float>%c1
[x86] Regenerate a bunch more avx512 test cases using my script to have tighter, more strict FileCheck assertions. Some of these I really like as they show case exactly what instruction sequences come out of these microscopic functionality tests. llvm-svn: 218936
2014-10-03 08:50:03 +08:00
}