2018-10-03 10:21:30 +08:00
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//=== lib/CodeGen/GlobalISel/AArch64PreLegalizerCombiner.cpp --------------===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2018-10-03 10:21:30 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass does combining of machine instructions at the generic MI level,
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// before the legalizer.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64TargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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2019-08-07 01:18:29 +08:00
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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2018-10-03 10:21:30 +08:00
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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2019-09-09 18:04:23 +08:00
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#include "llvm/CodeGen/MachineDominators.h"
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2018-10-03 10:21:30 +08:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "aarch64-prelegalizer-combiner"
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using namespace llvm;
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using namespace MIPatternMatch;
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2019-10-03 05:13:07 +08:00
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#define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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#include "AArch64GenGICombiner.inc"
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#undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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2018-10-03 10:21:30 +08:00
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namespace {
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2019-10-03 05:13:07 +08:00
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#define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
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#include "AArch64GenGICombiner.inc"
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#undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
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2018-10-03 10:21:30 +08:00
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class AArch64PreLegalizerCombinerInfo : public CombinerInfo {
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GISelKnownBits *KB;
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MachineDominatorTree *MDT;
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2018-10-03 10:21:30 +08:00
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public:
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2019-10-03 05:13:07 +08:00
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AArch64GenPreLegalizerCombinerHelper Generated;
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AArch64PreLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
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GISelKnownBits *KB, MachineDominatorTree *MDT)
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: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
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/*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
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KB(KB), MDT(MDT) {
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if (!Generated.parseCommandLineOption())
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report_fatal_error("Invalid rule identifier");
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}
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2018-12-06 04:14:52 +08:00
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virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
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MachineIRBuilder &B) const override;
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};
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2018-12-06 04:14:52 +08:00
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bool AArch64PreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
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MachineInstr &MI,
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MachineIRBuilder &B) const {
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CombinerHelper Helper(Observer, B, KB, MDT);
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switch (MI.getOpcode()) {
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case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
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switch (MI.getIntrinsicID()) {
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case Intrinsic::memcpy:
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case Intrinsic::memmove:
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case Intrinsic::memset: {
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2019-08-06 04:02:52 +08:00
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// If we're at -O0 set a maxlen of 32 to inline, otherwise let the other
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// heuristics decide.
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unsigned MaxLen = EnableOpt ? 0 : 32;
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// Try to inline memcpy type calls if optimizations are enabled.
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return (!EnableMinSize) ? Helper.tryCombineMemCpyFamily(MI, MaxLen)
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: false;
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}
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default:
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break;
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}
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2018-10-03 10:21:30 +08:00
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}
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2019-12-18 20:35:08 +08:00
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if (Generated.tryCombineAll(Observer, MI, B, Helper))
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return true;
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2019-12-18 20:26:31 +08:00
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switch (MI.getOpcode()) {
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case TargetOpcode::G_CONCAT_VECTORS:
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return Helper.tryCombineConcatVectors(MI);
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case TargetOpcode::G_SHUFFLE_VECTOR:
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return Helper.tryCombineShuffleVector(MI);
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}
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2018-10-03 10:21:30 +08:00
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return false;
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}
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2019-10-03 05:13:07 +08:00
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#define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
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#include "AArch64GenGICombiner.inc"
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#undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
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2018-10-03 10:21:30 +08:00
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// Pass boilerplate
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// ================
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class AArch64PreLegalizerCombiner : public MachineFunctionPass {
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public:
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static char ID;
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2019-09-09 18:04:23 +08:00
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AArch64PreLegalizerCombiner(bool IsOptNone = false);
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2018-10-03 10:21:30 +08:00
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StringRef getPassName() const override { return "AArch64PreLegalizerCombiner"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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private:
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bool IsOptNone;
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};
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2019-10-17 07:53:35 +08:00
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} // end anonymous namespace
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void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.setPreservesCFG();
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getSelectionDAGFallbackAnalysisUsage(AU);
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AU.addRequired<GISelKnownBitsAnalysis>();
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AU.addPreserved<GISelKnownBitsAnalysis>();
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if (!IsOptNone) {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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2018-10-03 10:21:30 +08:00
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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2019-09-09 18:04:23 +08:00
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AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner(bool IsOptNone)
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: MachineFunctionPass(ID), IsOptNone(IsOptNone) {
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initializeAArch64PreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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}
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bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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auto *TPC = &getAnalysis<TargetPassConfig>();
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const Function &F = MF.getFunction();
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bool EnableOpt =
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MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
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GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
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MachineDominatorTree *MDT =
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IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
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AArch64PreLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
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F.hasMinSize(), KB, MDT);
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Combiner C(PCInfo, TPC);
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return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
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}
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char AArch64PreLegalizerCombiner::ID = 0;
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INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE,
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"Combine AArch64 machine instrs before legalization",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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2019-08-07 01:18:29 +08:00
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INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
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2018-10-03 10:21:30 +08:00
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INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE,
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"Combine AArch64 machine instrs before legalization", false,
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false)
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namespace llvm {
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2019-09-09 18:04:23 +08:00
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FunctionPass *createAArch64PreLegalizeCombiner(bool IsOptNone) {
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return new AArch64PreLegalizerCombiner(IsOptNone);
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2018-10-03 10:21:30 +08:00
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}
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} // end namespace llvm
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