2019-03-18 04:36:12 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
2021-01-07 01:35:52 +08:00
|
|
|
; RUN: llc -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s --check-prefix=VI
|
|
|
|
|
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX9
|
2016-11-11 00:02:37 +08:00
|
|
|
|
|
|
|
|
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_test_imax_sge_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-LABEL: v_test_imax_sge_i16:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 1, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
[AMDGPU] Remove dubious logic in bidirectional list scheduler
Summary:
pickNodeBidirectional tried to compare the best top candidate and the
best bottom candidate by examining TopCand.Reason and BotCand.Reason.
This is unsound because, after calling pickNodeFromQueue, Cand.Reason
does not reflect the most important reason why Cand was chosen. Rather
it reflects the most recent reason why it beat some other potential
candidate, which could have been for some low priority tie breaker
reason.
I have seen this cause problems where TopCand is a good candidate, but
because TopCand.Reason is ORDER (which is very low priority) it is
repeatedly ignored in favour of a mediocre BotCand. This is not how
bidirectional scheduling is supposed to work.
To fix this I changed the code to always compare TopCand and BotCand
directly, like the generic implementation of pickNodeBidirectional does.
This removes some uncommented AMDGPU-specific logic; if this logic turns
out to be important then perhaps it could be moved into an override of
tryCandidate instead.
Graphics shader benchmarking on gfx10 shows a lot more positive than
negative effects from this change.
Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB
Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
|
|
|
; VI-NEXT: flat_load_ushort v0, v[0:1]
|
|
|
|
|
; VI-NEXT: flat_load_ushort v1, v[2:3]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s5
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
2020-10-16 15:09:38 +08:00
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
[AMDGPU] Remove dubious logic in bidirectional list scheduler
Summary:
pickNodeBidirectional tried to compare the best top candidate and the
best bottom candidate by examining TopCand.Reason and BotCand.Reason.
This is unsound because, after calling pickNodeFromQueue, Cand.Reason
does not reflect the most important reason why Cand was chosen. Rather
it reflects the most recent reason why it beat some other potential
candidate, which could have been for some low priority tie breaker
reason.
I have seen this cause problems where TopCand is a good candidate, but
because TopCand.Reason is ORDER (which is very low priority) it is
repeatedly ignored in favour of a mediocre BotCand. This is not how
bidirectional scheduling is supposed to work.
To fix this I changed the code to always compare TopCand and BotCand
directly, like the generic implementation of pickNodeBidirectional does.
This removes some uncommented AMDGPU-specific logic; if this logic turns
out to be important then perhaps it could be moved into an override of
tryCandidate instead.
Graphics shader benchmarking on gfx10 shows a lot more positive than
negative effects from this change.
Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB
Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
|
|
|
; VI-NEXT: v_max_i16_e32 v0, v0, v1
|
|
|
|
|
; VI-NEXT: flat_store_short v[4:5], v0
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: v_test_imax_sge_i16:
|
|
|
|
|
; GFX9: ; %bb.0:
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: global_load_ushort v1, v0, s[6:7]
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: global_load_ushort v2, v0, s[2:3]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_max_i16_e32 v1, v1, v2
|
|
|
|
|
; GFX9-NEXT: global_store_short v0, v1, s[4:5]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_endpgm
|
2016-11-11 00:02:37 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
|
|
|
%gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
|
|
|
|
|
%outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
|
|
|
|
|
%a = load i16, i16 addrspace(1)* %gep0, align 4
|
|
|
|
|
%b = load i16, i16 addrspace(1)* %gep1, align 4
|
|
|
|
|
%cmp = icmp sge i16 %a, %b
|
|
|
|
|
%val = select i1 %cmp, i16 %a, i16 %b
|
|
|
|
|
store i16 %val, i16 addrspace(1)* %outgep, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-28 06:15:25 +08:00
|
|
|
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_test_imax_sge_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %aptr, <2 x i16> addrspace(1)* %bptr) nounwind {
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-LABEL: v_test_imax_sge_v2i16:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
2020-01-07 23:43:46 +08:00
|
|
|
; VI-NEXT: flat_load_dword v5, v[0:1]
|
|
|
|
|
; VI-NEXT: flat_load_dword v2, v[2:3]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
2020-10-16 15:09:38 +08:00
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
2020-01-07 23:43:46 +08:00
|
|
|
; VI-NEXT: v_max_i16_e32 v3, v5, v2
|
|
|
|
|
; VI-NEXT: v_max_i16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
|
|
|
; VI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
|
|
|
; VI-NEXT: flat_store_dword v[0:1], v2
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: v_test_imax_sge_v2i16:
|
|
|
|
|
; GFX9: ; %bb.0:
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: global_load_dword v2, v0, s[2:3]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_pk_max_i16 v1, v1, v2
|
|
|
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_endpgm
|
2017-02-28 06:15:25 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
|
|
|
%gep0 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%gep1 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %bptr, i32 %tid
|
|
|
|
|
%outgep = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
|
|
|
|
|
%a = load <2 x i16>, <2 x i16> addrspace(1)* %gep0, align 4
|
|
|
|
|
%b = load <2 x i16>, <2 x i16> addrspace(1)* %gep1, align 4
|
|
|
|
|
%cmp = icmp sge <2 x i16> %a, %b
|
|
|
|
|
%val = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b
|
|
|
|
|
store <2 x i16> %val, <2 x i16> addrspace(1)* %outgep, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_test_imax_sge_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(1)* %aptr, <3 x i16> addrspace(1)* %bptr) nounwind {
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-LABEL: v_test_imax_sge_v3i16:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
2020-01-07 23:43:46 +08:00
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 3, v0
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr
Summary:
The typo has been present since memOpsHaveSameBasePtr was introduced in
r313208.
It caused SIInstrInfo::shouldClusterMemOps to cluster more mem ops than
it was supposed to.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71616
2019-12-18 00:09:02 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
2020-01-07 23:43:46 +08:00
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v6
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr
Summary:
The typo has been present since memOpsHaveSameBasePtr was introduced in
r313208.
It caused SIInstrInfo::shouldClusterMemOps to cluster more mem ops than
it was supposed to.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71616
2019-12-18 00:09:02 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
2020-01-07 23:43:46 +08:00
|
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v6
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
2020-01-07 23:43:46 +08:00
|
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 4, v0
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
|
|
|
|
|
; VI-NEXT: flat_load_ushort v4, v[4:5]
|
|
|
|
|
; VI-NEXT: flat_load_dword v5, v[0:1]
|
[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr
Summary:
The typo has been present since memOpsHaveSameBasePtr was introduced in
r313208.
It caused SIInstrInfo::shouldClusterMemOps to cluster more mem ops than
it was supposed to.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71616
2019-12-18 00:09:02 +08:00
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v2
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
|
2020-01-07 23:43:46 +08:00
|
|
|
; VI-NEXT: flat_load_dword v7, v[2:3]
|
|
|
|
|
; VI-NEXT: flat_load_ushort v8, v[0:1]
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v6
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
|
2020-10-16 15:09:38 +08:00
|
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
2020-01-07 23:43:46 +08:00
|
|
|
; VI-NEXT: v_max_i16_e32 v6, v5, v7
|
|
|
|
|
; VI-NEXT: v_max_i16_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
2020-10-16 15:09:38 +08:00
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
2020-01-07 23:43:46 +08:00
|
|
|
; VI-NEXT: v_max_i16_e32 v4, v4, v8
|
|
|
|
|
; VI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
|
|
|
; VI-NEXT: flat_store_short v[2:3], v4
|
|
|
|
|
; VI-NEXT: flat_store_dword v[0:1], v5
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: v_test_imax_sge_v3i16:
|
|
|
|
|
; GFX9: ; %bb.0:
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
|
|
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: global_load_short_d16 v1, v0, s[2:3] offset:4
|
|
|
|
|
; GFX9-NEXT: s_nop 0
|
|
|
|
|
; GFX9-NEXT: global_load_dword v3, v0, s[2:3]
|
|
|
|
|
; GFX9-NEXT: s_nop 0
|
[Scheduling] Implement a new way to cluster loads/stores
Before calling target hook to determine if two loads/stores are clusterable,
we put them into different groups to avoid fake cluster due to dependency.
For now, we are putting the loads/stores into the same group if they have
the same predecessor. We assume that, if two loads/stores have the same
predecessor, it is likely that, they didn't have dependency for each other.
However, one SUnit might have several predecessors and for now, we just
pick up the first predecessor that has non-data/non-artificial dependency,
which is too arbitrary. And we are struggling to fix it.
So, I am proposing some better implementation.
1. Collect all the loads/stores that has memory info first to reduce the complexity.
2. Sort these loads/stores so that we can stop the seeking as early as possible.
3. For each load/store, seeking for the first non-dependency instruction with the
sorted order, and check if they can cluster or not.
Reviewed By: Jay Foad
Differential Revision: https://reviews.llvm.org/D85517
2020-08-26 20:26:21 +08:00
|
|
|
; GFX9-NEXT: global_load_short_d16 v2, v0, s[6:7] offset:4
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: s_nop 0
|
[Scheduling] Implement a new way to cluster loads/stores
Before calling target hook to determine if two loads/stores are clusterable,
we put them into different groups to avoid fake cluster due to dependency.
For now, we are putting the loads/stores into the same group if they have
the same predecessor. We assume that, if two loads/stores have the same
predecessor, it is likely that, they didn't have dependency for each other.
However, one SUnit might have several predecessors and for now, we just
pick up the first predecessor that has non-data/non-artificial dependency,
which is too arbitrary. And we are struggling to fix it.
So, I am proposing some better implementation.
1. Collect all the loads/stores that has memory info first to reduce the complexity.
2. Sort these loads/stores so that we can stop the seeking as early as possible.
3. For each load/store, seeking for the first non-dependency instruction with the
sorted order, and check if they can cluster or not.
Reviewed By: Jay Foad
Differential Revision: https://reviews.llvm.org/D85517
2020-08-26 20:26:21 +08:00
|
|
|
; GFX9-NEXT: global_load_dword v4, v0, s[6:7]
|
|
|
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_pk_max_i16 v1, v2, v1
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
[Scheduling] Implement a new way to cluster loads/stores
Before calling target hook to determine if two loads/stores are clusterable,
we put them into different groups to avoid fake cluster due to dependency.
For now, we are putting the loads/stores into the same group if they have
the same predecessor. We assume that, if two loads/stores have the same
predecessor, it is likely that, they didn't have dependency for each other.
However, one SUnit might have several predecessors and for now, we just
pick up the first predecessor that has non-data/non-artificial dependency,
which is too arbitrary. And we are struggling to fix it.
So, I am proposing some better implementation.
1. Collect all the loads/stores that has memory info first to reduce the complexity.
2. Sort these loads/stores so that we can stop the seeking as early as possible.
3. For each load/store, seeking for the first non-dependency instruction with the
sorted order, and check if they can cluster or not.
Reviewed By: Jay Foad
Differential Revision: https://reviews.llvm.org/D85517
2020-08-26 20:26:21 +08:00
|
|
|
; GFX9-NEXT: v_pk_max_i16 v3, v4, v3
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: global_store_short v0, v1, s[4:5] offset:4
|
|
|
|
|
; GFX9-NEXT: global_store_dword v0, v3, s[4:5]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_endpgm
|
2017-02-28 06:15:25 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
|
|
|
%gep0 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%gep1 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %bptr, i32 %tid
|
|
|
|
|
%outgep = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %out, i32 %tid
|
|
|
|
|
%a = load <3 x i16>, <3 x i16> addrspace(1)* %gep0, align 4
|
|
|
|
|
%b = load <3 x i16>, <3 x i16> addrspace(1)* %gep1, align 4
|
|
|
|
|
%cmp = icmp sge <3 x i16> %a, %b
|
|
|
|
|
%val = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
|
|
|
|
|
store <3 x i16> %val, <3 x i16> addrspace(1)* %outgep, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-11 00:02:37 +08:00
|
|
|
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_test_imax_sge_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %aptr, <4 x i16> addrspace(1)* %bptr) nounwind {
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-LABEL: v_test_imax_sge_v4i16:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
|
|
|
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
|
[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr
Summary:
The typo has been present since memOpsHaveSameBasePtr was introduced in
r313208.
It caused SIInstrInfo::shouldClusterMemOps to cluster more mem ops than
it was supposed to.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71616
2019-12-18 00:09:02 +08:00
|
|
|
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s5
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
2020-10-16 15:09:38 +08:00
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-NEXT: v_max_i16_e32 v6, v1, v3
|
|
|
|
|
; VI-NEXT: v_max_i16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
|
|
|
; VI-NEXT: v_max_i16_e32 v3, v0, v2
|
|
|
|
|
; VI-NEXT: v_max_i16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
|
|
|
; VI-NEXT: v_or_b32_e32 v1, v6, v1
|
|
|
|
|
; VI-NEXT: v_or_b32_e32 v0, v3, v0
|
|
|
|
|
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
|
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: v_test_imax_sge_v4i16:
|
|
|
|
|
; GFX9: ; %bb.0:
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7]
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; GFX9-NEXT: v_pk_max_i16 v1, v1, v3
|
|
|
|
|
; GFX9-NEXT: v_pk_max_i16 v0, v0, v2
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_endpgm
|
2016-11-11 00:02:37 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
|
|
|
%gep0 = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%gep1 = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %bptr, i32 %tid
|
|
|
|
|
%outgep = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %out, i32 %tid
|
|
|
|
|
%a = load <4 x i16>, <4 x i16> addrspace(1)* %gep0, align 4
|
|
|
|
|
%b = load <4 x i16>, <4 x i16> addrspace(1)* %gep1, align 4
|
|
|
|
|
%cmp = icmp sge <4 x i16> %a, %b
|
|
|
|
|
%val = select <4 x i1> %cmp, <4 x i16> %a, <4 x i16> %b
|
|
|
|
|
store <4 x i16> %val, <4 x i16> addrspace(1)* %outgep, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_test_imax_sgt_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-LABEL: v_test_imax_sgt_i16:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 1, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
[AMDGPU] Remove dubious logic in bidirectional list scheduler
Summary:
pickNodeBidirectional tried to compare the best top candidate and the
best bottom candidate by examining TopCand.Reason and BotCand.Reason.
This is unsound because, after calling pickNodeFromQueue, Cand.Reason
does not reflect the most important reason why Cand was chosen. Rather
it reflects the most recent reason why it beat some other potential
candidate, which could have been for some low priority tie breaker
reason.
I have seen this cause problems where TopCand is a good candidate, but
because TopCand.Reason is ORDER (which is very low priority) it is
repeatedly ignored in favour of a mediocre BotCand. This is not how
bidirectional scheduling is supposed to work.
To fix this I changed the code to always compare TopCand and BotCand
directly, like the generic implementation of pickNodeBidirectional does.
This removes some uncommented AMDGPU-specific logic; if this logic turns
out to be important then perhaps it could be moved into an override of
tryCandidate instead.
Graphics shader benchmarking on gfx10 shows a lot more positive than
negative effects from this change.
Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB
Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
|
|
|
; VI-NEXT: flat_load_ushort v0, v[0:1]
|
|
|
|
|
; VI-NEXT: flat_load_ushort v1, v[2:3]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s5
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
2020-10-16 15:09:38 +08:00
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
[AMDGPU] Remove dubious logic in bidirectional list scheduler
Summary:
pickNodeBidirectional tried to compare the best top candidate and the
best bottom candidate by examining TopCand.Reason and BotCand.Reason.
This is unsound because, after calling pickNodeFromQueue, Cand.Reason
does not reflect the most important reason why Cand was chosen. Rather
it reflects the most recent reason why it beat some other potential
candidate, which could have been for some low priority tie breaker
reason.
I have seen this cause problems where TopCand is a good candidate, but
because TopCand.Reason is ORDER (which is very low priority) it is
repeatedly ignored in favour of a mediocre BotCand. This is not how
bidirectional scheduling is supposed to work.
To fix this I changed the code to always compare TopCand and BotCand
directly, like the generic implementation of pickNodeBidirectional does.
This removes some uncommented AMDGPU-specific logic; if this logic turns
out to be important then perhaps it could be moved into an override of
tryCandidate instead.
Graphics shader benchmarking on gfx10 shows a lot more positive than
negative effects from this change.
Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB
Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
|
|
|
; VI-NEXT: v_max_i16_e32 v0, v0, v1
|
|
|
|
|
; VI-NEXT: flat_store_short v[4:5], v0
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: v_test_imax_sgt_i16:
|
|
|
|
|
; GFX9: ; %bb.0:
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: global_load_ushort v1, v0, s[6:7]
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: global_load_ushort v2, v0, s[2:3]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_max_i16_e32 v1, v1, v2
|
|
|
|
|
; GFX9-NEXT: global_store_short v0, v1, s[4:5]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_endpgm
|
2016-11-11 00:02:37 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
|
|
|
%gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
|
|
|
|
|
%outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
|
|
|
|
|
%a = load i16, i16 addrspace(1)* %gep0, align 4
|
|
|
|
|
%b = load i16, i16 addrspace(1)* %gep1, align 4
|
|
|
|
|
%cmp = icmp sgt i16 %a, %b
|
|
|
|
|
%val = select i1 %cmp, i16 %a, i16 %b
|
|
|
|
|
store i16 %val, i16 addrspace(1)* %outgep, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_test_umax_uge_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-LABEL: v_test_umax_uge_i16:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 1, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
[AMDGPU] Remove dubious logic in bidirectional list scheduler
Summary:
pickNodeBidirectional tried to compare the best top candidate and the
best bottom candidate by examining TopCand.Reason and BotCand.Reason.
This is unsound because, after calling pickNodeFromQueue, Cand.Reason
does not reflect the most important reason why Cand was chosen. Rather
it reflects the most recent reason why it beat some other potential
candidate, which could have been for some low priority tie breaker
reason.
I have seen this cause problems where TopCand is a good candidate, but
because TopCand.Reason is ORDER (which is very low priority) it is
repeatedly ignored in favour of a mediocre BotCand. This is not how
bidirectional scheduling is supposed to work.
To fix this I changed the code to always compare TopCand and BotCand
directly, like the generic implementation of pickNodeBidirectional does.
This removes some uncommented AMDGPU-specific logic; if this logic turns
out to be important then perhaps it could be moved into an override of
tryCandidate instead.
Graphics shader benchmarking on gfx10 shows a lot more positive than
negative effects from this change.
Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB
Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
|
|
|
; VI-NEXT: flat_load_ushort v0, v[0:1]
|
|
|
|
|
; VI-NEXT: flat_load_ushort v1, v[2:3]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s5
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
2020-10-16 15:09:38 +08:00
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
[AMDGPU] Remove dubious logic in bidirectional list scheduler
Summary:
pickNodeBidirectional tried to compare the best top candidate and the
best bottom candidate by examining TopCand.Reason and BotCand.Reason.
This is unsound because, after calling pickNodeFromQueue, Cand.Reason
does not reflect the most important reason why Cand was chosen. Rather
it reflects the most recent reason why it beat some other potential
candidate, which could have been for some low priority tie breaker
reason.
I have seen this cause problems where TopCand is a good candidate, but
because TopCand.Reason is ORDER (which is very low priority) it is
repeatedly ignored in favour of a mediocre BotCand. This is not how
bidirectional scheduling is supposed to work.
To fix this I changed the code to always compare TopCand and BotCand
directly, like the generic implementation of pickNodeBidirectional does.
This removes some uncommented AMDGPU-specific logic; if this logic turns
out to be important then perhaps it could be moved into an override of
tryCandidate instead.
Graphics shader benchmarking on gfx10 shows a lot more positive than
negative effects from this change.
Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB
Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
|
|
|
; VI-NEXT: v_max_u16_e32 v0, v0, v1
|
|
|
|
|
; VI-NEXT: flat_store_short v[4:5], v0
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: v_test_umax_uge_i16:
|
|
|
|
|
; GFX9: ; %bb.0:
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: global_load_ushort v1, v0, s[6:7]
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: global_load_ushort v2, v0, s[2:3]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_max_u16_e32 v1, v1, v2
|
|
|
|
|
; GFX9-NEXT: global_store_short v0, v1, s[4:5]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_endpgm
|
2016-11-11 00:02:37 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
|
|
|
%gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
|
|
|
|
|
%outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
|
|
|
|
|
%a = load i16, i16 addrspace(1)* %gep0, align 4
|
|
|
|
|
%b = load i16, i16 addrspace(1)* %gep1, align 4
|
|
|
|
|
%cmp = icmp uge i16 %a, %b
|
|
|
|
|
%val = select i1 %cmp, i16 %a, i16 %b
|
|
|
|
|
store i16 %val, i16 addrspace(1)* %outgep, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_test_umax_ugt_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-LABEL: v_test_umax_ugt_i16:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 1, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
[AMDGPU] Remove dubious logic in bidirectional list scheduler
Summary:
pickNodeBidirectional tried to compare the best top candidate and the
best bottom candidate by examining TopCand.Reason and BotCand.Reason.
This is unsound because, after calling pickNodeFromQueue, Cand.Reason
does not reflect the most important reason why Cand was chosen. Rather
it reflects the most recent reason why it beat some other potential
candidate, which could have been for some low priority tie breaker
reason.
I have seen this cause problems where TopCand is a good candidate, but
because TopCand.Reason is ORDER (which is very low priority) it is
repeatedly ignored in favour of a mediocre BotCand. This is not how
bidirectional scheduling is supposed to work.
To fix this I changed the code to always compare TopCand and BotCand
directly, like the generic implementation of pickNodeBidirectional does.
This removes some uncommented AMDGPU-specific logic; if this logic turns
out to be important then perhaps it could be moved into an override of
tryCandidate instead.
Graphics shader benchmarking on gfx10 shows a lot more positive than
negative effects from this change.
Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB
Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
|
|
|
; VI-NEXT: flat_load_ushort v0, v[0:1]
|
|
|
|
|
; VI-NEXT: flat_load_ushort v1, v[2:3]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s5
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
2020-10-16 15:09:38 +08:00
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
[AMDGPU] Remove dubious logic in bidirectional list scheduler
Summary:
pickNodeBidirectional tried to compare the best top candidate and the
best bottom candidate by examining TopCand.Reason and BotCand.Reason.
This is unsound because, after calling pickNodeFromQueue, Cand.Reason
does not reflect the most important reason why Cand was chosen. Rather
it reflects the most recent reason why it beat some other potential
candidate, which could have been for some low priority tie breaker
reason.
I have seen this cause problems where TopCand is a good candidate, but
because TopCand.Reason is ORDER (which is very low priority) it is
repeatedly ignored in favour of a mediocre BotCand. This is not how
bidirectional scheduling is supposed to work.
To fix this I changed the code to always compare TopCand and BotCand
directly, like the generic implementation of pickNodeBidirectional does.
This removes some uncommented AMDGPU-specific logic; if this logic turns
out to be important then perhaps it could be moved into an override of
tryCandidate instead.
Graphics shader benchmarking on gfx10 shows a lot more positive than
negative effects from this change.
Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB
Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
|
|
|
; VI-NEXT: v_max_u16_e32 v0, v0, v1
|
|
|
|
|
; VI-NEXT: flat_store_short v[4:5], v0
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: v_test_umax_ugt_i16:
|
|
|
|
|
; GFX9: ; %bb.0:
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: global_load_ushort v1, v0, s[6:7]
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: global_load_ushort v2, v0, s[2:3]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_max_u16_e32 v1, v1, v2
|
|
|
|
|
; GFX9-NEXT: global_store_short v0, v1, s[4:5]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_endpgm
|
2016-11-11 00:02:37 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
|
|
|
%gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
|
|
|
|
|
%outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
|
|
|
|
|
%a = load i16, i16 addrspace(1)* %gep0, align 4
|
|
|
|
|
%b = load i16, i16 addrspace(1)* %gep1, align 4
|
|
|
|
|
%cmp = icmp ugt i16 %a, %b
|
|
|
|
|
%val = select i1 %cmp, i16 %a, i16 %b
|
|
|
|
|
store i16 %val, i16 addrspace(1)* %outgep, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2017-02-28 06:15:25 +08:00
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_test_umax_ugt_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %aptr, <2 x i16> addrspace(1)* %bptr) nounwind {
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-LABEL: v_test_umax_ugt_v2i16:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
2020-01-07 23:43:46 +08:00
|
|
|
; VI-NEXT: flat_load_dword v5, v[0:1]
|
|
|
|
|
; VI-NEXT: flat_load_dword v2, v[2:3]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v4
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
2020-10-16 15:09:38 +08:00
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
2020-01-07 23:43:46 +08:00
|
|
|
; VI-NEXT: v_max_u16_e32 v3, v5, v2
|
|
|
|
|
; VI-NEXT: v_max_u16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
|
|
|
; VI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
|
|
|
; VI-NEXT: flat_store_dword v[0:1], v2
|
2019-03-18 04:36:12 +08:00
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: v_test_umax_ugt_v2i16:
|
|
|
|
|
; GFX9: ; %bb.0:
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
2020-12-01 01:06:35 +08:00
|
|
|
; GFX9-NEXT: global_load_dword v2, v0, s[2:3]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
2020-08-14 04:51:07 +08:00
|
|
|
; GFX9-NEXT: v_pk_max_u16 v1, v1, v2
|
|
|
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
2019-03-18 04:36:12 +08:00
|
|
|
; GFX9-NEXT: s_endpgm
|
2017-02-28 06:15:25 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
|
|
|
%gep0 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%gep1 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %bptr, i32 %tid
|
|
|
|
|
%outgep = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
|
|
|
|
|
%a = load <2 x i16>, <2 x i16> addrspace(1)* %gep0, align 4
|
|
|
|
|
%b = load <2 x i16>, <2 x i16> addrspace(1)* %gep1, align 4
|
|
|
|
|
%cmp = icmp ugt <2 x i16> %a, %b
|
|
|
|
|
%val = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b
|
|
|
|
|
store <2 x i16> %val, <2 x i16> addrspace(1)* %outgep, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|