2012-07-27 02:38:11 +08:00
|
|
|
//===- lib/CodeGen/MachineTraceMetrics.cpp ----------------------*- C++ -*-===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2013-01-17 09:06:04 +08:00
|
|
|
#include "llvm/CodeGen/MachineTraceMetrics.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/ADT/PostOrderIterator.h"
|
|
|
|
#include "llvm/ADT/SparseSet.h"
|
2012-07-27 02:38:11 +08:00
|
|
|
#include "llvm/CodeGen/MachineBasicBlock.h"
|
|
|
|
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
|
|
|
|
#include "llvm/CodeGen/MachineLoopInfo.h"
|
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
|
|
#include "llvm/CodeGen/Passes.h"
|
2012-10-05 01:30:40 +08:00
|
|
|
#include "llvm/MC/MCSubtargetInfo.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/Support/Debug.h"
|
2013-04-03 01:49:51 +08:00
|
|
|
#include "llvm/Support/Format.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/Support/raw_ostream.h"
|
2012-07-27 02:38:11 +08:00
|
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
|
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
2012-10-05 01:30:40 +08:00
|
|
|
#include "llvm/Target/TargetSubtargetInfo.h"
|
2012-07-27 02:38:11 +08:00
|
|
|
|
|
|
|
using namespace llvm;
|
|
|
|
|
2014-04-22 10:02:50 +08:00
|
|
|
#define DEBUG_TYPE "machine-trace-metrics"
|
|
|
|
|
2012-07-27 02:38:11 +08:00
|
|
|
char MachineTraceMetrics::ID = 0;
|
|
|
|
char &llvm::MachineTraceMetricsID = MachineTraceMetrics::ID;
|
|
|
|
|
|
|
|
INITIALIZE_PASS_BEGIN(MachineTraceMetrics,
|
|
|
|
"machine-trace-metrics", "Machine Trace Metrics", false, true)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
|
|
|
|
INITIALIZE_PASS_END(MachineTraceMetrics,
|
|
|
|
"machine-trace-metrics", "Machine Trace Metrics", false, true)
|
|
|
|
|
|
|
|
MachineTraceMetrics::MachineTraceMetrics()
|
2014-04-14 08:51:57 +08:00
|
|
|
: MachineFunctionPass(ID), MF(nullptr), TII(nullptr), TRI(nullptr),
|
|
|
|
MRI(nullptr), Loops(nullptr) {
|
2014-04-13 00:15:53 +08:00
|
|
|
std::fill(std::begin(Ensembles), std::end(Ensembles), nullptr);
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void MachineTraceMetrics::getAnalysisUsage(AnalysisUsage &AU) const {
|
|
|
|
AU.setPreservesAll();
|
|
|
|
AU.addRequired<MachineBranchProbabilityInfo>();
|
|
|
|
AU.addRequired<MachineLoopInfo>();
|
|
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
|
|
}
|
|
|
|
|
2012-07-31 02:34:11 +08:00
|
|
|
bool MachineTraceMetrics::runOnMachineFunction(MachineFunction &Func) {
|
|
|
|
MF = &Func;
|
2015-01-27 15:31:29 +08:00
|
|
|
const TargetSubtargetInfo &ST = MF->getSubtarget();
|
|
|
|
TII = ST.getInstrInfo();
|
|
|
|
TRI = ST.getRegisterInfo();
|
2012-07-31 02:34:11 +08:00
|
|
|
MRI = &MF->getRegInfo();
|
2012-07-27 02:38:11 +08:00
|
|
|
Loops = &getAnalysis<MachineLoopInfo>();
|
2014-09-03 01:43:54 +08:00
|
|
|
SchedModel.init(ST.getSchedModel(), &ST, TII);
|
2012-07-31 02:34:11 +08:00
|
|
|
BlockInfo.resize(MF->getNumBlockIDs());
|
2013-04-03 01:49:51 +08:00
|
|
|
ProcResourceCycles.resize(MF->getNumBlockIDs() *
|
|
|
|
SchedModel.getNumProcResourceKinds());
|
2012-07-27 02:38:11 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineTraceMetrics::releaseMemory() {
|
2014-04-14 08:51:57 +08:00
|
|
|
MF = nullptr;
|
2012-07-27 02:38:11 +08:00
|
|
|
BlockInfo.clear();
|
|
|
|
for (unsigned i = 0; i != TS_NumStrategies; ++i) {
|
|
|
|
delete Ensembles[i];
|
2014-04-14 08:51:57 +08:00
|
|
|
Ensembles[i] = nullptr;
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Fixed block information
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// The number of instructions in a basic block and the CPU resources used by
|
|
|
|
// those instructions don't depend on any given trace strategy.
|
|
|
|
|
|
|
|
/// Compute the resource usage in basic block MBB.
|
|
|
|
const MachineTraceMetrics::FixedBlockInfo*
|
|
|
|
MachineTraceMetrics::getResources(const MachineBasicBlock *MBB) {
|
|
|
|
assert(MBB && "No basic block");
|
|
|
|
FixedBlockInfo *FBI = &BlockInfo[MBB->getNumber()];
|
|
|
|
if (FBI->hasResources())
|
|
|
|
return FBI;
|
|
|
|
|
|
|
|
// Compute resource usage in the block.
|
|
|
|
FBI->HasCalls = false;
|
|
|
|
unsigned InstrCount = 0;
|
2013-04-03 01:49:51 +08:00
|
|
|
|
|
|
|
// Add up per-processor resource cycles as well.
|
|
|
|
unsigned PRKinds = SchedModel.getNumProcResourceKinds();
|
|
|
|
SmallVector<unsigned, 32> PRCycles(PRKinds);
|
|
|
|
|
2014-05-01 06:17:38 +08:00
|
|
|
for (const auto &MI : *MBB) {
|
|
|
|
if (MI.isTransient())
|
2012-07-27 02:38:11 +08:00
|
|
|
continue;
|
|
|
|
++InstrCount;
|
2014-05-01 06:17:38 +08:00
|
|
|
if (MI.isCall())
|
2012-07-27 02:38:11 +08:00
|
|
|
FBI->HasCalls = true;
|
2013-04-03 01:49:51 +08:00
|
|
|
|
|
|
|
// Count processor resources used.
|
2013-04-03 06:27:45 +08:00
|
|
|
if (!SchedModel.hasInstrSchedModel())
|
|
|
|
continue;
|
2014-05-01 06:17:38 +08:00
|
|
|
const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI);
|
2013-04-03 01:49:51 +08:00
|
|
|
if (!SC->isValid())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
for (TargetSchedModel::ProcResIter
|
|
|
|
PI = SchedModel.getWriteProcResBegin(SC),
|
|
|
|
PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
|
|
|
|
assert(PI->ProcResourceIdx < PRKinds && "Bad processor resource kind");
|
|
|
|
PRCycles[PI->ProcResourceIdx] += PI->Cycles;
|
|
|
|
}
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
FBI->InstrCount = InstrCount;
|
2013-04-03 01:49:51 +08:00
|
|
|
|
|
|
|
// Scale the resource cycles so they are comparable.
|
|
|
|
unsigned PROffset = MBB->getNumber() * PRKinds;
|
|
|
|
for (unsigned K = 0; K != PRKinds; ++K)
|
|
|
|
ProcResourceCycles[PROffset + K] =
|
|
|
|
PRCycles[K] * SchedModel.getResourceFactor(K);
|
|
|
|
|
2012-07-27 02:38:11 +08:00
|
|
|
return FBI;
|
|
|
|
}
|
|
|
|
|
2013-04-03 01:49:51 +08:00
|
|
|
ArrayRef<unsigned>
|
|
|
|
MachineTraceMetrics::getProcResourceCycles(unsigned MBBNum) const {
|
|
|
|
assert(BlockInfo[MBBNum].hasResources() &&
|
|
|
|
"getResources() must be called before getProcResourceCycles()");
|
|
|
|
unsigned PRKinds = SchedModel.getNumProcResourceKinds();
|
2013-04-03 06:27:45 +08:00
|
|
|
assert((MBBNum+1) * PRKinds <= ProcResourceCycles.size());
|
2014-08-27 13:25:25 +08:00
|
|
|
return makeArrayRef(ProcResourceCycles.data() + MBBNum * PRKinds, PRKinds);
|
2013-04-03 01:49:51 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2012-07-27 02:38:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Ensemble utility functions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
MachineTraceMetrics::Ensemble::Ensemble(MachineTraceMetrics *ct)
|
2012-08-01 04:25:13 +08:00
|
|
|
: MTM(*ct) {
|
|
|
|
BlockInfo.resize(MTM.BlockInfo.size());
|
2013-04-03 01:49:51 +08:00
|
|
|
unsigned PRKinds = MTM.SchedModel.getNumProcResourceKinds();
|
|
|
|
ProcResourceDepths.resize(MTM.BlockInfo.size() * PRKinds);
|
|
|
|
ProcResourceHeights.resize(MTM.BlockInfo.size() * PRKinds);
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Virtual destructor serves as an anchor.
|
|
|
|
MachineTraceMetrics::Ensemble::~Ensemble() {}
|
|
|
|
|
2012-07-31 02:34:11 +08:00
|
|
|
const MachineLoop*
|
|
|
|
MachineTraceMetrics::Ensemble::getLoopFor(const MachineBasicBlock *MBB) const {
|
2012-08-01 04:25:13 +08:00
|
|
|
return MTM.Loops->getLoopFor(MBB);
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Update resource-related information in the TraceBlockInfo for MBB.
|
|
|
|
// Only update resources related to the trace above MBB.
|
|
|
|
void MachineTraceMetrics::Ensemble::
|
|
|
|
computeDepthResources(const MachineBasicBlock *MBB) {
|
|
|
|
TraceBlockInfo *TBI = &BlockInfo[MBB->getNumber()];
|
2013-04-03 01:49:51 +08:00
|
|
|
unsigned PRKinds = MTM.SchedModel.getNumProcResourceKinds();
|
|
|
|
unsigned PROffset = MBB->getNumber() * PRKinds;
|
2012-07-27 02:38:11 +08:00
|
|
|
|
|
|
|
// Compute resources from trace above. The top block is simple.
|
|
|
|
if (!TBI->Pred) {
|
|
|
|
TBI->InstrDepth = 0;
|
2012-07-28 07:58:36 +08:00
|
|
|
TBI->Head = MBB->getNumber();
|
2013-04-03 01:49:51 +08:00
|
|
|
std::fill(ProcResourceDepths.begin() + PROffset,
|
|
|
|
ProcResourceDepths.begin() + PROffset + PRKinds, 0);
|
2012-07-27 02:38:11 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Compute from the block above. A post-order traversal ensures the
|
|
|
|
// predecessor is always computed first.
|
2013-04-03 01:49:51 +08:00
|
|
|
unsigned PredNum = TBI->Pred->getNumber();
|
|
|
|
TraceBlockInfo *PredTBI = &BlockInfo[PredNum];
|
2012-07-27 02:38:11 +08:00
|
|
|
assert(PredTBI->hasValidDepth() && "Trace above has not been computed yet");
|
2012-08-01 04:25:13 +08:00
|
|
|
const FixedBlockInfo *PredFBI = MTM.getResources(TBI->Pred);
|
2012-07-27 02:38:11 +08:00
|
|
|
TBI->InstrDepth = PredTBI->InstrDepth + PredFBI->InstrCount;
|
2012-07-28 07:58:36 +08:00
|
|
|
TBI->Head = PredTBI->Head;
|
2013-04-03 01:49:51 +08:00
|
|
|
|
|
|
|
// Compute per-resource depths.
|
|
|
|
ArrayRef<unsigned> PredPRDepths = getProcResourceDepths(PredNum);
|
|
|
|
ArrayRef<unsigned> PredPRCycles = MTM.getProcResourceCycles(PredNum);
|
|
|
|
for (unsigned K = 0; K != PRKinds; ++K)
|
|
|
|
ProcResourceDepths[PROffset + K] = PredPRDepths[K] + PredPRCycles[K];
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Update resource-related information in the TraceBlockInfo for MBB.
|
|
|
|
// Only update resources related to the trace below MBB.
|
|
|
|
void MachineTraceMetrics::Ensemble::
|
|
|
|
computeHeightResources(const MachineBasicBlock *MBB) {
|
|
|
|
TraceBlockInfo *TBI = &BlockInfo[MBB->getNumber()];
|
2013-04-03 01:49:51 +08:00
|
|
|
unsigned PRKinds = MTM.SchedModel.getNumProcResourceKinds();
|
|
|
|
unsigned PROffset = MBB->getNumber() * PRKinds;
|
2012-07-27 02:38:11 +08:00
|
|
|
|
|
|
|
// Compute resources for the current block.
|
2012-08-01 04:25:13 +08:00
|
|
|
TBI->InstrHeight = MTM.getResources(MBB)->InstrCount;
|
2013-04-03 01:49:51 +08:00
|
|
|
ArrayRef<unsigned> PRCycles = MTM.getProcResourceCycles(MBB->getNumber());
|
2012-07-27 02:38:11 +08:00
|
|
|
|
|
|
|
// The trace tail is done.
|
2012-07-28 07:58:36 +08:00
|
|
|
if (!TBI->Succ) {
|
|
|
|
TBI->Tail = MBB->getNumber();
|
2013-04-03 01:49:51 +08:00
|
|
|
std::copy(PRCycles.begin(), PRCycles.end(),
|
|
|
|
ProcResourceHeights.begin() + PROffset);
|
2012-07-27 02:38:11 +08:00
|
|
|
return;
|
2012-07-28 07:58:36 +08:00
|
|
|
}
|
2012-07-27 02:38:11 +08:00
|
|
|
|
|
|
|
// Compute from the block below. A post-order traversal ensures the
|
|
|
|
// predecessor is always computed first.
|
2013-04-03 01:49:51 +08:00
|
|
|
unsigned SuccNum = TBI->Succ->getNumber();
|
|
|
|
TraceBlockInfo *SuccTBI = &BlockInfo[SuccNum];
|
2012-07-27 02:38:11 +08:00
|
|
|
assert(SuccTBI->hasValidHeight() && "Trace below has not been computed yet");
|
|
|
|
TBI->InstrHeight += SuccTBI->InstrHeight;
|
2012-07-28 07:58:36 +08:00
|
|
|
TBI->Tail = SuccTBI->Tail;
|
2013-04-03 01:49:51 +08:00
|
|
|
|
|
|
|
// Compute per-resource heights.
|
|
|
|
ArrayRef<unsigned> SuccPRHeights = getProcResourceHeights(SuccNum);
|
|
|
|
for (unsigned K = 0; K != PRKinds; ++K)
|
|
|
|
ProcResourceHeights[PROffset + K] = SuccPRHeights[K] + PRCycles[K];
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Check if depth resources for MBB are valid and return the TBI.
|
|
|
|
// Return NULL if the resources have been invalidated.
|
|
|
|
const MachineTraceMetrics::TraceBlockInfo*
|
|
|
|
MachineTraceMetrics::Ensemble::
|
|
|
|
getDepthResources(const MachineBasicBlock *MBB) const {
|
|
|
|
const TraceBlockInfo *TBI = &BlockInfo[MBB->getNumber()];
|
2014-04-14 08:51:57 +08:00
|
|
|
return TBI->hasValidDepth() ? TBI : nullptr;
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Check if height resources for MBB are valid and return the TBI.
|
|
|
|
// Return NULL if the resources have been invalidated.
|
|
|
|
const MachineTraceMetrics::TraceBlockInfo*
|
|
|
|
MachineTraceMetrics::Ensemble::
|
|
|
|
getHeightResources(const MachineBasicBlock *MBB) const {
|
|
|
|
const TraceBlockInfo *TBI = &BlockInfo[MBB->getNumber()];
|
2014-04-14 08:51:57 +08:00
|
|
|
return TBI->hasValidHeight() ? TBI : nullptr;
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
|
2013-04-03 01:49:51 +08:00
|
|
|
/// Get an array of processor resource depths for MBB. Indexed by processor
|
|
|
|
/// resource kind, this array contains the scaled processor resources consumed
|
|
|
|
/// by all blocks preceding MBB in its trace. It does not include instructions
|
|
|
|
/// in MBB.
|
|
|
|
///
|
|
|
|
/// Compare TraceBlockInfo::InstrDepth.
|
|
|
|
ArrayRef<unsigned>
|
|
|
|
MachineTraceMetrics::Ensemble::
|
|
|
|
getProcResourceDepths(unsigned MBBNum) const {
|
|
|
|
unsigned PRKinds = MTM.SchedModel.getNumProcResourceKinds();
|
2013-04-03 06:27:45 +08:00
|
|
|
assert((MBBNum+1) * PRKinds <= ProcResourceDepths.size());
|
2014-08-27 13:25:25 +08:00
|
|
|
return makeArrayRef(ProcResourceDepths.data() + MBBNum * PRKinds, PRKinds);
|
2013-04-03 01:49:51 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Get an array of processor resource heights for MBB. Indexed by processor
|
|
|
|
/// resource kind, this array contains the scaled processor resources consumed
|
|
|
|
/// by this block and all blocks following it in its trace.
|
|
|
|
///
|
|
|
|
/// Compare TraceBlockInfo::InstrHeight.
|
|
|
|
ArrayRef<unsigned>
|
|
|
|
MachineTraceMetrics::Ensemble::
|
|
|
|
getProcResourceHeights(unsigned MBBNum) const {
|
|
|
|
unsigned PRKinds = MTM.SchedModel.getNumProcResourceKinds();
|
2013-04-03 06:27:45 +08:00
|
|
|
assert((MBBNum+1) * PRKinds <= ProcResourceHeights.size());
|
2014-08-27 13:25:25 +08:00
|
|
|
return makeArrayRef(ProcResourceHeights.data() + MBBNum * PRKinds, PRKinds);
|
2013-04-03 01:49:51 +08:00
|
|
|
}
|
|
|
|
|
2012-07-27 02:38:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Trace Selection Strategies
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// A trace selection strategy is implemented as a sub-class of Ensemble. The
|
|
|
|
// trace through a block B is computed by two DFS traversals of the CFG
|
|
|
|
// starting from B. One upwards, and one downwards. During the upwards DFS,
|
|
|
|
// pickTracePred() is called on the post-ordered blocks. During the downwards
|
|
|
|
// DFS, pickTraceSucc() is called in a post-order.
|
|
|
|
//
|
|
|
|
|
2012-07-31 07:15:10 +08:00
|
|
|
// We never allow traces that leave loops, but we do allow traces to enter
|
|
|
|
// nested loops. We also never allow traces to contain back-edges.
|
|
|
|
//
|
|
|
|
// This means that a loop header can never appear above the center block of a
|
|
|
|
// trace, except as the trace head. Below the center block, loop exiting edges
|
|
|
|
// are banned.
|
|
|
|
//
|
|
|
|
// Return true if an edge from the From loop to the To loop is leaving a loop.
|
|
|
|
// Either of To and From can be null.
|
|
|
|
static bool isExitingLoop(const MachineLoop *From, const MachineLoop *To) {
|
|
|
|
return From && !From->contains(To);
|
|
|
|
}
|
|
|
|
|
2012-07-27 02:38:11 +08:00
|
|
|
// MinInstrCountEnsemble - Pick the trace that executes the least number of
|
|
|
|
// instructions.
|
|
|
|
namespace {
|
|
|
|
class MinInstrCountEnsemble : public MachineTraceMetrics::Ensemble {
|
2014-03-07 17:26:03 +08:00
|
|
|
const char *getName() const override { return "MinInstr"; }
|
|
|
|
const MachineBasicBlock *pickTracePred(const MachineBasicBlock*) override;
|
|
|
|
const MachineBasicBlock *pickTraceSucc(const MachineBasicBlock*) override;
|
2012-07-27 02:38:11 +08:00
|
|
|
|
|
|
|
public:
|
2012-08-01 04:25:13 +08:00
|
|
|
MinInstrCountEnsemble(MachineTraceMetrics *mtm)
|
|
|
|
: MachineTraceMetrics::Ensemble(mtm) {}
|
2012-07-27 02:38:11 +08:00
|
|
|
};
|
2015-06-23 17:49:53 +08:00
|
|
|
}
|
2012-07-27 02:38:11 +08:00
|
|
|
|
|
|
|
// Select the preferred predecessor for MBB.
|
|
|
|
const MachineBasicBlock*
|
|
|
|
MinInstrCountEnsemble::pickTracePred(const MachineBasicBlock *MBB) {
|
|
|
|
if (MBB->pred_empty())
|
2014-04-14 08:51:57 +08:00
|
|
|
return nullptr;
|
2012-07-31 02:34:11 +08:00
|
|
|
const MachineLoop *CurLoop = getLoopFor(MBB);
|
2012-07-27 02:38:11 +08:00
|
|
|
// Don't leave loops, and never follow back-edges.
|
|
|
|
if (CurLoop && MBB == CurLoop->getHeader())
|
2014-04-14 08:51:57 +08:00
|
|
|
return nullptr;
|
2012-08-01 04:25:13 +08:00
|
|
|
unsigned CurCount = MTM.getResources(MBB)->InstrCount;
|
2014-04-14 08:51:57 +08:00
|
|
|
const MachineBasicBlock *Best = nullptr;
|
2012-07-27 02:38:11 +08:00
|
|
|
unsigned BestDepth = 0;
|
2015-05-22 01:22:45 +08:00
|
|
|
for (const MachineBasicBlock *Pred : MBB->predecessors()) {
|
2012-07-31 05:10:27 +08:00
|
|
|
const MachineTraceMetrics::TraceBlockInfo *PredTBI =
|
|
|
|
getDepthResources(Pred);
|
2012-08-09 06:12:01 +08:00
|
|
|
// Ignore cycles that aren't natural loops.
|
|
|
|
if (!PredTBI)
|
|
|
|
continue;
|
2012-07-27 02:38:11 +08:00
|
|
|
// Pick the predecessor that would give this block the smallest InstrDepth.
|
|
|
|
unsigned Depth = PredTBI->InstrDepth + CurCount;
|
|
|
|
if (!Best || Depth < BestDepth)
|
|
|
|
Best = Pred, BestDepth = Depth;
|
|
|
|
}
|
|
|
|
return Best;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Select the preferred successor for MBB.
|
|
|
|
const MachineBasicBlock*
|
|
|
|
MinInstrCountEnsemble::pickTraceSucc(const MachineBasicBlock *MBB) {
|
|
|
|
if (MBB->pred_empty())
|
2014-04-14 08:51:57 +08:00
|
|
|
return nullptr;
|
2012-07-31 02:34:11 +08:00
|
|
|
const MachineLoop *CurLoop = getLoopFor(MBB);
|
2014-04-14 08:51:57 +08:00
|
|
|
const MachineBasicBlock *Best = nullptr;
|
2012-07-27 02:38:11 +08:00
|
|
|
unsigned BestHeight = 0;
|
2015-05-22 01:22:45 +08:00
|
|
|
for (const MachineBasicBlock *Succ : MBB->successors()) {
|
2012-07-27 02:38:11 +08:00
|
|
|
// Don't consider back-edges.
|
|
|
|
if (CurLoop && Succ == CurLoop->getHeader())
|
|
|
|
continue;
|
2012-07-31 07:15:10 +08:00
|
|
|
// Don't consider successors exiting CurLoop.
|
|
|
|
if (isExitingLoop(CurLoop, getLoopFor(Succ)))
|
2012-07-27 02:38:11 +08:00
|
|
|
continue;
|
2012-07-31 05:10:27 +08:00
|
|
|
const MachineTraceMetrics::TraceBlockInfo *SuccTBI =
|
|
|
|
getHeightResources(Succ);
|
2012-08-09 06:12:01 +08:00
|
|
|
// Ignore cycles that aren't natural loops.
|
|
|
|
if (!SuccTBI)
|
|
|
|
continue;
|
2012-07-27 02:38:11 +08:00
|
|
|
// Pick the successor that would give this block the smallest InstrHeight.
|
|
|
|
unsigned Height = SuccTBI->InstrHeight;
|
|
|
|
if (!Best || Height < BestHeight)
|
|
|
|
Best = Succ, BestHeight = Height;
|
|
|
|
}
|
|
|
|
return Best;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Get an Ensemble sub-class for the requested trace strategy.
|
|
|
|
MachineTraceMetrics::Ensemble *
|
|
|
|
MachineTraceMetrics::getEnsemble(MachineTraceMetrics::Strategy strategy) {
|
|
|
|
assert(strategy < TS_NumStrategies && "Invalid trace strategy enum");
|
|
|
|
Ensemble *&E = Ensembles[strategy];
|
|
|
|
if (E)
|
|
|
|
return E;
|
|
|
|
|
|
|
|
// Allocate new Ensemble on demand.
|
|
|
|
switch (strategy) {
|
|
|
|
case TS_MinInstrCount: return (E = new MinInstrCountEnsemble(this));
|
|
|
|
default: llvm_unreachable("Invalid trace strategy enum");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineTraceMetrics::invalidate(const MachineBasicBlock *MBB) {
|
|
|
|
DEBUG(dbgs() << "Invalidate traces through BB#" << MBB->getNumber() << '\n');
|
|
|
|
BlockInfo[MBB->getNumber()].invalidate();
|
|
|
|
for (unsigned i = 0; i != TS_NumStrategies; ++i)
|
|
|
|
if (Ensembles[i])
|
|
|
|
Ensembles[i]->invalidate(MBB);
|
|
|
|
}
|
|
|
|
|
2012-07-31 04:57:50 +08:00
|
|
|
void MachineTraceMetrics::verifyAnalysis() const {
|
2012-07-31 07:15:12 +08:00
|
|
|
if (!MF)
|
|
|
|
return;
|
2012-07-31 02:34:11 +08:00
|
|
|
#ifndef NDEBUG
|
|
|
|
assert(BlockInfo.size() == MF->getNumBlockIDs() && "Outdated BlockInfo size");
|
|
|
|
for (unsigned i = 0; i != TS_NumStrategies; ++i)
|
|
|
|
if (Ensembles[i])
|
|
|
|
Ensembles[i]->verify();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2012-07-27 02:38:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Trace building
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// Traces are built by two CFG traversals. To avoid recomputing too much, use a
|
|
|
|
// set abstraction that confines the search to the current loop, and doesn't
|
|
|
|
// revisit blocks.
|
|
|
|
|
|
|
|
namespace {
|
|
|
|
struct LoopBounds {
|
|
|
|
MutableArrayRef<MachineTraceMetrics::TraceBlockInfo> Blocks;
|
2012-08-09 06:12:01 +08:00
|
|
|
SmallPtrSet<const MachineBasicBlock*, 8> Visited;
|
2012-07-27 02:38:11 +08:00
|
|
|
const MachineLoopInfo *Loops;
|
|
|
|
bool Downward;
|
|
|
|
LoopBounds(MutableArrayRef<MachineTraceMetrics::TraceBlockInfo> blocks,
|
2012-07-31 07:15:10 +08:00
|
|
|
const MachineLoopInfo *loops)
|
|
|
|
: Blocks(blocks), Loops(loops), Downward(false) {}
|
2012-07-27 02:38:11 +08:00
|
|
|
};
|
2015-06-23 17:49:53 +08:00
|
|
|
}
|
2012-07-27 02:38:11 +08:00
|
|
|
|
|
|
|
// Specialize po_iterator_storage in order to prune the post-order traversal so
|
|
|
|
// it is limited to the current loop and doesn't traverse the loop back edges.
|
|
|
|
namespace llvm {
|
|
|
|
template<>
|
|
|
|
class po_iterator_storage<LoopBounds, true> {
|
|
|
|
LoopBounds &LB;
|
|
|
|
public:
|
|
|
|
po_iterator_storage(LoopBounds &lb) : LB(lb) {}
|
|
|
|
void finishPostorder(const MachineBasicBlock*) {}
|
|
|
|
|
|
|
|
bool insertEdge(const MachineBasicBlock *From, const MachineBasicBlock *To) {
|
|
|
|
// Skip already visited To blocks.
|
|
|
|
MachineTraceMetrics::TraceBlockInfo &TBI = LB.Blocks[To->getNumber()];
|
|
|
|
if (LB.Downward ? TBI.hasValidHeight() : TBI.hasValidDepth())
|
|
|
|
return false;
|
2012-07-31 07:15:10 +08:00
|
|
|
// From is null once when To is the trace center block.
|
2012-08-09 06:12:01 +08:00
|
|
|
if (From) {
|
|
|
|
if (const MachineLoop *FromLoop = LB.Loops->getLoopFor(From)) {
|
|
|
|
// Don't follow backedges, don't leave FromLoop when going upwards.
|
|
|
|
if ((LB.Downward ? To : From) == FromLoop->getHeader())
|
|
|
|
return false;
|
|
|
|
// Don't leave FromLoop.
|
|
|
|
if (isExitingLoop(FromLoop, LB.Loops->getLoopFor(To)))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// To is a new block. Mark the block as visited in case the CFG has cycles
|
|
|
|
// that MachineLoopInfo didn't recognize as a natural loop.
|
2014-11-19 15:49:26 +08:00
|
|
|
return LB.Visited.insert(To).second;
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
};
|
2015-06-23 17:49:53 +08:00
|
|
|
}
|
2012-07-27 02:38:11 +08:00
|
|
|
|
|
|
|
/// Compute the trace through MBB.
|
|
|
|
void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) {
|
|
|
|
DEBUG(dbgs() << "Computing " << getName() << " trace through BB#"
|
|
|
|
<< MBB->getNumber() << '\n');
|
|
|
|
// Set up loop bounds for the backwards post-order traversal.
|
2012-08-01 04:25:13 +08:00
|
|
|
LoopBounds Bounds(BlockInfo, MTM.Loops);
|
2012-07-27 02:38:11 +08:00
|
|
|
|
|
|
|
// Run an upwards post-order search for the trace start.
|
|
|
|
Bounds.Downward = false;
|
2012-08-09 06:12:01 +08:00
|
|
|
Bounds.Visited.clear();
|
2015-04-16 01:41:42 +08:00
|
|
|
for (auto I : inverse_post_order_ext(MBB, Bounds)) {
|
2012-07-27 02:38:11 +08:00
|
|
|
DEBUG(dbgs() << " pred for BB#" << I->getNumber() << ": ");
|
|
|
|
TraceBlockInfo &TBI = BlockInfo[I->getNumber()];
|
|
|
|
// All the predecessors have been visited, pick the preferred one.
|
2015-04-16 01:41:42 +08:00
|
|
|
TBI.Pred = pickTracePred(I);
|
2012-07-27 02:38:11 +08:00
|
|
|
DEBUG({
|
|
|
|
if (TBI.Pred)
|
|
|
|
dbgs() << "BB#" << TBI.Pred->getNumber() << '\n';
|
|
|
|
else
|
|
|
|
dbgs() << "null\n";
|
|
|
|
});
|
|
|
|
// The trace leading to I is now known, compute the depth resources.
|
2015-04-16 01:41:42 +08:00
|
|
|
computeDepthResources(I);
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Run a downwards post-order search for the trace end.
|
|
|
|
Bounds.Downward = true;
|
2012-08-09 06:12:01 +08:00
|
|
|
Bounds.Visited.clear();
|
2015-04-16 01:41:42 +08:00
|
|
|
for (auto I : post_order_ext(MBB, Bounds)) {
|
2012-07-27 02:38:11 +08:00
|
|
|
DEBUG(dbgs() << " succ for BB#" << I->getNumber() << ": ");
|
|
|
|
TraceBlockInfo &TBI = BlockInfo[I->getNumber()];
|
|
|
|
// All the successors have been visited, pick the preferred one.
|
2015-04-16 01:41:42 +08:00
|
|
|
TBI.Succ = pickTraceSucc(I);
|
2012-07-27 02:38:11 +08:00
|
|
|
DEBUG({
|
2012-07-31 07:15:10 +08:00
|
|
|
if (TBI.Succ)
|
2012-07-27 02:38:11 +08:00
|
|
|
dbgs() << "BB#" << TBI.Succ->getNumber() << '\n';
|
|
|
|
else
|
|
|
|
dbgs() << "null\n";
|
|
|
|
});
|
|
|
|
// The trace leaving I is now known, compute the height resources.
|
2015-04-16 01:41:42 +08:00
|
|
|
computeHeightResources(I);
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Invalidate traces through BadMBB.
|
|
|
|
void
|
|
|
|
MachineTraceMetrics::Ensemble::invalidate(const MachineBasicBlock *BadMBB) {
|
|
|
|
SmallVector<const MachineBasicBlock*, 16> WorkList;
|
|
|
|
TraceBlockInfo &BadTBI = BlockInfo[BadMBB->getNumber()];
|
|
|
|
|
|
|
|
// Invalidate height resources of blocks above MBB.
|
|
|
|
if (BadTBI.hasValidHeight()) {
|
|
|
|
BadTBI.invalidateHeight();
|
|
|
|
WorkList.push_back(BadMBB);
|
|
|
|
do {
|
|
|
|
const MachineBasicBlock *MBB = WorkList.pop_back_val();
|
|
|
|
DEBUG(dbgs() << "Invalidate BB#" << MBB->getNumber() << ' ' << getName()
|
|
|
|
<< " height.\n");
|
|
|
|
// Find any MBB predecessors that have MBB as their preferred successor.
|
|
|
|
// They are the only ones that need to be invalidated.
|
2015-07-07 00:27:35 +08:00
|
|
|
for (const MachineBasicBlock *Pred : MBB->predecessors()) {
|
|
|
|
TraceBlockInfo &TBI = BlockInfo[Pred->getNumber()];
|
2012-07-31 01:36:49 +08:00
|
|
|
if (!TBI.hasValidHeight())
|
|
|
|
continue;
|
|
|
|
if (TBI.Succ == MBB) {
|
2012-07-27 02:38:11 +08:00
|
|
|
TBI.invalidateHeight();
|
2015-07-07 00:27:35 +08:00
|
|
|
WorkList.push_back(Pred);
|
2012-07-31 01:36:49 +08:00
|
|
|
continue;
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
2012-07-31 01:36:49 +08:00
|
|
|
// Verify that TBI.Succ is actually a *I successor.
|
2015-07-07 00:27:35 +08:00
|
|
|
assert((!TBI.Succ || Pred->isSuccessor(TBI.Succ)) && "CFG changed");
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
} while (!WorkList.empty());
|
|
|
|
}
|
|
|
|
|
|
|
|
// Invalidate depth resources of blocks below MBB.
|
|
|
|
if (BadTBI.hasValidDepth()) {
|
|
|
|
BadTBI.invalidateDepth();
|
|
|
|
WorkList.push_back(BadMBB);
|
|
|
|
do {
|
|
|
|
const MachineBasicBlock *MBB = WorkList.pop_back_val();
|
|
|
|
DEBUG(dbgs() << "Invalidate BB#" << MBB->getNumber() << ' ' << getName()
|
|
|
|
<< " depth.\n");
|
|
|
|
// Find any MBB successors that have MBB as their preferred predecessor.
|
|
|
|
// They are the only ones that need to be invalidated.
|
2015-07-07 00:27:35 +08:00
|
|
|
for (const MachineBasicBlock *Succ : MBB->successors()) {
|
|
|
|
TraceBlockInfo &TBI = BlockInfo[Succ->getNumber()];
|
2012-07-31 01:36:49 +08:00
|
|
|
if (!TBI.hasValidDepth())
|
|
|
|
continue;
|
|
|
|
if (TBI.Pred == MBB) {
|
2012-07-27 02:38:11 +08:00
|
|
|
TBI.invalidateDepth();
|
2015-07-07 00:27:35 +08:00
|
|
|
WorkList.push_back(Succ);
|
2012-07-31 01:36:49 +08:00
|
|
|
continue;
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
2012-07-31 01:36:49 +08:00
|
|
|
// Verify that TBI.Pred is actually a *I predecessor.
|
2015-07-07 00:27:35 +08:00
|
|
|
assert((!TBI.Pred || Succ->isPredecessor(TBI.Pred)) && "CFG changed");
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
} while (!WorkList.empty());
|
|
|
|
}
|
2012-08-01 04:44:38 +08:00
|
|
|
|
|
|
|
// Clear any per-instruction data. We only have to do this for BadMBB itself
|
|
|
|
// because the instructions in that block may change. Other blocks may be
|
|
|
|
// invalidated, but their instructions will stay the same, so there is no
|
|
|
|
// need to erase the Cycle entries. They will be overwritten when we
|
|
|
|
// recompute.
|
2014-05-01 06:17:38 +08:00
|
|
|
for (const auto &I : *BadMBB)
|
|
|
|
Cycles.erase(&I);
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
|
2012-07-31 02:34:11 +08:00
|
|
|
void MachineTraceMetrics::Ensemble::verify() const {
|
|
|
|
#ifndef NDEBUG
|
2012-08-01 04:25:13 +08:00
|
|
|
assert(BlockInfo.size() == MTM.MF->getNumBlockIDs() &&
|
2012-07-31 02:34:11 +08:00
|
|
|
"Outdated BlockInfo size");
|
|
|
|
for (unsigned Num = 0, e = BlockInfo.size(); Num != e; ++Num) {
|
|
|
|
const TraceBlockInfo &TBI = BlockInfo[Num];
|
|
|
|
if (TBI.hasValidDepth() && TBI.Pred) {
|
2012-08-01 04:25:13 +08:00
|
|
|
const MachineBasicBlock *MBB = MTM.MF->getBlockNumbered(Num);
|
2012-07-31 02:34:11 +08:00
|
|
|
assert(MBB->isPredecessor(TBI.Pred) && "CFG doesn't match trace");
|
|
|
|
assert(BlockInfo[TBI.Pred->getNumber()].hasValidDepth() &&
|
|
|
|
"Trace is broken, depth should have been invalidated.");
|
|
|
|
const MachineLoop *Loop = getLoopFor(MBB);
|
|
|
|
assert(!(Loop && MBB == Loop->getHeader()) && "Trace contains backedge");
|
|
|
|
}
|
|
|
|
if (TBI.hasValidHeight() && TBI.Succ) {
|
2012-08-01 04:25:13 +08:00
|
|
|
const MachineBasicBlock *MBB = MTM.MF->getBlockNumbered(Num);
|
2012-07-31 02:34:11 +08:00
|
|
|
assert(MBB->isSuccessor(TBI.Succ) && "CFG doesn't match trace");
|
|
|
|
assert(BlockInfo[TBI.Succ->getNumber()].hasValidHeight() &&
|
|
|
|
"Trace is broken, height should have been invalidated.");
|
|
|
|
const MachineLoop *Loop = getLoopFor(MBB);
|
|
|
|
const MachineLoop *SuccLoop = getLoopFor(TBI.Succ);
|
|
|
|
assert(!(Loop && Loop == SuccLoop && TBI.Succ == Loop->getHeader()) &&
|
|
|
|
"Trace contains backedge");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
2012-07-27 02:38:11 +08:00
|
|
|
|
2012-08-01 04:44:38 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Data Dependencies
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// Compute the depth and height of each instruction based on data dependencies
|
|
|
|
// and instruction latencies. These cycle numbers assume that the CPU can issue
|
|
|
|
// an infinite number of instructions per cycle as long as their dependencies
|
|
|
|
// are ready.
|
|
|
|
|
|
|
|
// A data dependency is represented as a defining MI and operand numbers on the
|
|
|
|
// defining and using MI.
|
|
|
|
namespace {
|
|
|
|
struct DataDep {
|
|
|
|
const MachineInstr *DefMI;
|
|
|
|
unsigned DefOp;
|
|
|
|
unsigned UseOp;
|
2012-08-02 00:02:59 +08:00
|
|
|
|
|
|
|
DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp)
|
|
|
|
: DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {}
|
|
|
|
|
|
|
|
/// Create a DataDep from an SSA form virtual register.
|
|
|
|
DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp)
|
|
|
|
: UseOp(UseOp) {
|
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(VirtReg));
|
|
|
|
MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg);
|
|
|
|
assert(!DefI.atEnd() && "Register has no defs");
|
2014-03-14 07:12:04 +08:00
|
|
|
DefMI = DefI->getParent();
|
2012-08-02 00:02:59 +08:00
|
|
|
DefOp = DefI.getOperandNo();
|
|
|
|
assert((++DefI).atEnd() && "Register has multiple defs");
|
|
|
|
}
|
2012-08-01 04:44:38 +08:00
|
|
|
};
|
2015-06-23 17:49:53 +08:00
|
|
|
}
|
2012-08-01 04:44:38 +08:00
|
|
|
|
|
|
|
// Get the input data dependencies that must be ready before UseMI can issue.
|
|
|
|
// Return true if UseMI has any physreg operands.
|
|
|
|
static bool getDataDeps(const MachineInstr *UseMI,
|
|
|
|
SmallVectorImpl<DataDep> &Deps,
|
|
|
|
const MachineRegisterInfo *MRI) {
|
|
|
|
bool HasPhysRegs = false;
|
2015-05-29 10:56:46 +08:00
|
|
|
for (MachineInstr::const_mop_iterator I = UseMI->operands_begin(),
|
|
|
|
E = UseMI->operands_end(); I != E; ++I) {
|
|
|
|
const MachineOperand &MO = *I;
|
|
|
|
if (!MO.isReg())
|
2012-08-01 04:44:38 +08:00
|
|
|
continue;
|
2015-05-29 10:56:46 +08:00
|
|
|
unsigned Reg = MO.getReg();
|
2012-08-01 04:44:38 +08:00
|
|
|
if (!Reg)
|
|
|
|
continue;
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
|
|
HasPhysRegs = true;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
// Collect virtual register reads.
|
2015-05-29 10:56:46 +08:00
|
|
|
if (MO.readsReg())
|
|
|
|
Deps.push_back(DataDep(MRI, Reg, UseMI->getOperandNo(I)));
|
2012-08-01 04:44:38 +08:00
|
|
|
}
|
|
|
|
return HasPhysRegs;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Get the input data dependencies of a PHI instruction, using Pred as the
|
|
|
|
// preferred predecessor.
|
|
|
|
// This will add at most one dependency to Deps.
|
|
|
|
static void getPHIDeps(const MachineInstr *UseMI,
|
|
|
|
SmallVectorImpl<DataDep> &Deps,
|
|
|
|
const MachineBasicBlock *Pred,
|
|
|
|
const MachineRegisterInfo *MRI) {
|
|
|
|
// No predecessor at the beginning of a trace. Ignore dependencies.
|
|
|
|
if (!Pred)
|
|
|
|
return;
|
|
|
|
assert(UseMI->isPHI() && UseMI->getNumOperands() % 2 && "Bad PHI");
|
|
|
|
for (unsigned i = 1; i != UseMI->getNumOperands(); i += 2) {
|
|
|
|
if (UseMI->getOperand(i + 1).getMBB() == Pred) {
|
|
|
|
unsigned Reg = UseMI->getOperand(i).getReg();
|
2012-08-02 00:02:59 +08:00
|
|
|
Deps.push_back(DataDep(MRI, Reg, i));
|
2012-08-01 04:44:38 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Keep track of physreg data dependencies by recording each live register unit.
|
2012-08-02 06:36:00 +08:00
|
|
|
// Associate each regunit with an instruction operand. Depending on the
|
|
|
|
// direction instructions are scanned, it could be the operand that defined the
|
|
|
|
// regunit, or the highest operand to read the regunit.
|
2012-08-01 04:44:38 +08:00
|
|
|
namespace {
|
|
|
|
struct LiveRegUnit {
|
|
|
|
unsigned RegUnit;
|
2012-08-02 06:36:00 +08:00
|
|
|
unsigned Cycle;
|
|
|
|
const MachineInstr *MI;
|
|
|
|
unsigned Op;
|
2012-08-01 04:44:38 +08:00
|
|
|
|
|
|
|
unsigned getSparseSetIndex() const { return RegUnit; }
|
|
|
|
|
2014-04-14 08:51:57 +08:00
|
|
|
LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(nullptr), Op(0) {}
|
2012-08-01 04:44:38 +08:00
|
|
|
};
|
2015-06-23 17:49:53 +08:00
|
|
|
}
|
2012-08-01 04:44:38 +08:00
|
|
|
|
|
|
|
// Identify physreg dependencies for UseMI, and update the live regunit
|
|
|
|
// tracking set when scanning instructions downwards.
|
|
|
|
static void updatePhysDepsDownwards(const MachineInstr *UseMI,
|
|
|
|
SmallVectorImpl<DataDep> &Deps,
|
|
|
|
SparseSet<LiveRegUnit> &RegUnits,
|
|
|
|
const TargetRegisterInfo *TRI) {
|
|
|
|
SmallVector<unsigned, 8> Kills;
|
|
|
|
SmallVector<unsigned, 8> LiveDefOps;
|
|
|
|
|
2015-05-29 10:56:46 +08:00
|
|
|
for (MachineInstr::const_mop_iterator MI = UseMI->operands_begin(),
|
|
|
|
ME = UseMI->operands_end(); MI != ME; ++MI) {
|
|
|
|
const MachineOperand &MO = *MI;
|
|
|
|
if (!MO.isReg())
|
2012-08-01 04:44:38 +08:00
|
|
|
continue;
|
2015-05-29 10:56:46 +08:00
|
|
|
unsigned Reg = MO.getReg();
|
2012-08-01 04:44:38 +08:00
|
|
|
if (!TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
|
|
continue;
|
|
|
|
// Track live defs and kills for updating RegUnits.
|
2015-05-29 10:56:46 +08:00
|
|
|
if (MO.isDef()) {
|
|
|
|
if (MO.isDead())
|
2012-08-01 04:44:38 +08:00
|
|
|
Kills.push_back(Reg);
|
|
|
|
else
|
2015-05-29 10:56:46 +08:00
|
|
|
LiveDefOps.push_back(UseMI->getOperandNo(MI));
|
|
|
|
} else if (MO.isKill())
|
2012-08-01 04:44:38 +08:00
|
|
|
Kills.push_back(Reg);
|
|
|
|
// Identify dependencies.
|
2015-05-29 10:56:46 +08:00
|
|
|
if (!MO.readsReg())
|
2012-08-01 04:44:38 +08:00
|
|
|
continue;
|
|
|
|
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
|
|
|
|
SparseSet<LiveRegUnit>::iterator I = RegUnits.find(*Units);
|
|
|
|
if (I == RegUnits.end())
|
|
|
|
continue;
|
2015-05-29 10:56:46 +08:00
|
|
|
Deps.push_back(DataDep(I->MI, I->Op, UseMI->getOperandNo(MI)));
|
2012-08-01 04:44:38 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Update RegUnits to reflect live registers after UseMI.
|
|
|
|
// First kills.
|
|
|
|
for (unsigned i = 0, e = Kills.size(); i != e; ++i)
|
|
|
|
for (MCRegUnitIterator Units(Kills[i], TRI); Units.isValid(); ++Units)
|
|
|
|
RegUnits.erase(*Units);
|
|
|
|
|
|
|
|
// Second, live defs.
|
|
|
|
for (unsigned i = 0, e = LiveDefOps.size(); i != e; ++i) {
|
|
|
|
unsigned DefOp = LiveDefOps[i];
|
|
|
|
for (MCRegUnitIterator Units(UseMI->getOperand(DefOp).getReg(), TRI);
|
|
|
|
Units.isValid(); ++Units) {
|
|
|
|
LiveRegUnit &LRU = RegUnits[*Units];
|
2012-08-02 06:36:00 +08:00
|
|
|
LRU.MI = UseMI;
|
|
|
|
LRU.Op = DefOp;
|
2012-08-01 04:44:38 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-08-03 02:45:54 +08:00
|
|
|
/// The length of the critical path through a trace is the maximum of two path
|
|
|
|
/// lengths:
|
|
|
|
///
|
|
|
|
/// 1. The maximum height+depth over all instructions in the trace center block.
|
|
|
|
///
|
|
|
|
/// 2. The longest cross-block dependency chain. For small blocks, it is
|
|
|
|
/// possible that the critical path through the trace doesn't include any
|
|
|
|
/// instructions in the block.
|
|
|
|
///
|
|
|
|
/// This function computes the second number from the live-in list of the
|
|
|
|
/// center block.
|
|
|
|
unsigned MachineTraceMetrics::Ensemble::
|
|
|
|
computeCrossBlockCriticalPath(const TraceBlockInfo &TBI) {
|
|
|
|
assert(TBI.HasValidInstrDepths && "Missing depth info");
|
|
|
|
assert(TBI.HasValidInstrHeights && "Missing height info");
|
|
|
|
unsigned MaxLen = 0;
|
|
|
|
for (unsigned i = 0, e = TBI.LiveIns.size(); i != e; ++i) {
|
|
|
|
const LiveInReg &LIR = TBI.LiveIns[i];
|
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(LIR.Reg))
|
|
|
|
continue;
|
|
|
|
const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
|
|
|
|
// Ignore dependencies outside the current trace.
|
|
|
|
const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()];
|
2013-03-08 07:55:49 +08:00
|
|
|
if (!DefTBI.isUsefulDominator(TBI))
|
2012-08-03 02:45:54 +08:00
|
|
|
continue;
|
|
|
|
unsigned Len = LIR.Height + Cycles[DefMI].Depth;
|
|
|
|
MaxLen = std::max(MaxLen, Len);
|
|
|
|
}
|
|
|
|
return MaxLen;
|
|
|
|
}
|
|
|
|
|
2012-08-01 04:44:38 +08:00
|
|
|
/// Compute instruction depths for all instructions above or in MBB in its
|
|
|
|
/// trace. This assumes that the trace through MBB has already been computed.
|
|
|
|
void MachineTraceMetrics::Ensemble::
|
|
|
|
computeInstrDepths(const MachineBasicBlock *MBB) {
|
|
|
|
// The top of the trace may already be computed, and HasValidInstrDepths
|
|
|
|
// implies Head->HasValidInstrDepths, so we only need to start from the first
|
|
|
|
// block in the trace that needs to be recomputed.
|
|
|
|
SmallVector<const MachineBasicBlock*, 8> Stack;
|
|
|
|
do {
|
|
|
|
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
|
|
|
|
assert(TBI.hasValidDepth() && "Incomplete trace");
|
|
|
|
if (TBI.HasValidInstrDepths)
|
|
|
|
break;
|
|
|
|
Stack.push_back(MBB);
|
|
|
|
MBB = TBI.Pred;
|
|
|
|
} while (MBB);
|
|
|
|
|
|
|
|
// FIXME: If MBB is non-null at this point, it is the last pre-computed block
|
|
|
|
// in the trace. We should track any live-out physregs that were defined in
|
|
|
|
// the trace. This is quite rare in SSA form, typically created by CSE
|
|
|
|
// hoisting a compare.
|
|
|
|
SparseSet<LiveRegUnit> RegUnits;
|
|
|
|
RegUnits.setUniverse(MTM.TRI->getNumRegUnits());
|
|
|
|
|
|
|
|
// Go through trace blocks in top-down order, stopping after the center block.
|
|
|
|
SmallVector<DataDep, 8> Deps;
|
|
|
|
while (!Stack.empty()) {
|
|
|
|
MBB = Stack.pop_back_val();
|
2013-04-03 01:49:51 +08:00
|
|
|
DEBUG(dbgs() << "\nDepths for BB#" << MBB->getNumber() << ":\n");
|
2012-08-01 04:44:38 +08:00
|
|
|
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
|
|
|
|
TBI.HasValidInstrDepths = true;
|
2012-08-03 02:45:54 +08:00
|
|
|
TBI.CriticalPath = 0;
|
|
|
|
|
2013-04-03 01:49:51 +08:00
|
|
|
// Print out resource depths here as well.
|
|
|
|
DEBUG({
|
|
|
|
dbgs() << format("%7u Instructions\n", TBI.InstrDepth);
|
|
|
|
ArrayRef<unsigned> PRDepths = getProcResourceDepths(MBB->getNumber());
|
|
|
|
for (unsigned K = 0; K != PRDepths.size(); ++K)
|
|
|
|
if (PRDepths[K]) {
|
|
|
|
unsigned Factor = MTM.SchedModel.getResourceFactor(K);
|
|
|
|
dbgs() << format("%6uc @ ", MTM.getCycles(PRDepths[K]))
|
|
|
|
<< MTM.SchedModel.getProcResource(K)->Name << " ("
|
|
|
|
<< PRDepths[K]/Factor << " ops x" << Factor << ")\n";
|
|
|
|
}
|
|
|
|
});
|
|
|
|
|
2012-08-03 02:45:54 +08:00
|
|
|
// Also compute the critical path length through MBB when possible.
|
|
|
|
if (TBI.HasValidInstrHeights)
|
|
|
|
TBI.CriticalPath = computeCrossBlockCriticalPath(TBI);
|
|
|
|
|
2014-05-01 06:17:38 +08:00
|
|
|
for (const auto &UseMI : *MBB) {
|
2012-08-01 04:44:38 +08:00
|
|
|
// Collect all data dependencies.
|
|
|
|
Deps.clear();
|
2014-05-01 06:17:38 +08:00
|
|
|
if (UseMI.isPHI())
|
|
|
|
getPHIDeps(&UseMI, Deps, TBI.Pred, MTM.MRI);
|
|
|
|
else if (getDataDeps(&UseMI, Deps, MTM.MRI))
|
|
|
|
updatePhysDepsDownwards(&UseMI, Deps, RegUnits, MTM.TRI);
|
2012-08-01 04:44:38 +08:00
|
|
|
|
|
|
|
// Filter and process dependencies, computing the earliest issue cycle.
|
|
|
|
unsigned Cycle = 0;
|
2015-07-01 00:30:22 +08:00
|
|
|
for (const DataDep &Dep : Deps) {
|
2012-08-01 04:44:38 +08:00
|
|
|
const TraceBlockInfo&DepTBI =
|
|
|
|
BlockInfo[Dep.DefMI->getParent()->getNumber()];
|
|
|
|
// Ignore dependencies from outside the current trace.
|
2013-03-08 07:55:49 +08:00
|
|
|
if (!DepTBI.isUsefulDominator(TBI))
|
2012-08-01 04:44:38 +08:00
|
|
|
continue;
|
|
|
|
assert(DepTBI.HasValidInstrDepths && "Inconsistent dependency");
|
|
|
|
unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth;
|
|
|
|
// Add latency if DefMI is a real instruction. Transients get latency 0.
|
|
|
|
if (!Dep.DefMI->isTransient())
|
2012-10-05 01:30:40 +08:00
|
|
|
DepCycle += MTM.SchedModel
|
2014-05-01 06:17:38 +08:00
|
|
|
.computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp);
|
2012-08-01 04:44:38 +08:00
|
|
|
Cycle = std::max(Cycle, DepCycle);
|
|
|
|
}
|
|
|
|
// Remember the instruction depth.
|
2014-05-01 06:17:38 +08:00
|
|
|
InstrCycles &MICycles = Cycles[&UseMI];
|
2012-08-03 02:45:54 +08:00
|
|
|
MICycles.Depth = Cycle;
|
|
|
|
|
|
|
|
if (!TBI.HasValidInstrHeights) {
|
2014-05-01 06:17:38 +08:00
|
|
|
DEBUG(dbgs() << Cycle << '\t' << UseMI);
|
2012-08-03 02:45:54 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
// Update critical path length.
|
|
|
|
TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Height);
|
2014-05-01 06:17:38 +08:00
|
|
|
DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI);
|
2012-08-01 04:44:38 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-08-02 06:36:00 +08:00
|
|
|
// Identify physreg dependencies for MI when scanning instructions upwards.
|
|
|
|
// Return the issue height of MI after considering any live regunits.
|
|
|
|
// Height is the issue height computed from virtual register dependencies alone.
|
|
|
|
static unsigned updatePhysDepsUpwards(const MachineInstr *MI, unsigned Height,
|
|
|
|
SparseSet<LiveRegUnit> &RegUnits,
|
2012-10-05 01:30:40 +08:00
|
|
|
const TargetSchedModel &SchedModel,
|
2012-08-02 06:36:00 +08:00
|
|
|
const TargetInstrInfo *TII,
|
|
|
|
const TargetRegisterInfo *TRI) {
|
|
|
|
SmallVector<unsigned, 8> ReadOps;
|
2015-05-29 10:56:46 +08:00
|
|
|
|
|
|
|
for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
|
|
|
|
MOE = MI->operands_end(); MOI != MOE; ++MOI) {
|
|
|
|
const MachineOperand &MO = *MOI;
|
|
|
|
if (!MO.isReg())
|
2012-08-02 06:36:00 +08:00
|
|
|
continue;
|
2015-05-29 10:56:46 +08:00
|
|
|
unsigned Reg = MO.getReg();
|
2012-08-02 06:36:00 +08:00
|
|
|
if (!TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
|
|
continue;
|
2015-05-29 10:56:46 +08:00
|
|
|
if (MO.readsReg())
|
|
|
|
ReadOps.push_back(MI->getOperandNo(MOI));
|
|
|
|
if (!MO.isDef())
|
2012-08-02 06:36:00 +08:00
|
|
|
continue;
|
|
|
|
// This is a def of Reg. Remove corresponding entries from RegUnits, and
|
|
|
|
// update MI Height to consider the physreg dependencies.
|
|
|
|
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
|
|
|
|
SparseSet<LiveRegUnit>::iterator I = RegUnits.find(*Units);
|
|
|
|
if (I == RegUnits.end())
|
|
|
|
continue;
|
|
|
|
unsigned DepHeight = I->Cycle;
|
|
|
|
if (!MI->isTransient()) {
|
|
|
|
// We may not know the UseMI of this dependency, if it came from the
|
2012-10-05 01:30:40 +08:00
|
|
|
// live-in list. SchedModel can handle a NULL UseMI.
|
|
|
|
DepHeight += SchedModel
|
2015-05-29 10:56:46 +08:00
|
|
|
.computeOperandLatency(MI, MI->getOperandNo(MOI), I->MI, I->Op);
|
2012-08-02 06:36:00 +08:00
|
|
|
}
|
|
|
|
Height = std::max(Height, DepHeight);
|
|
|
|
// This regunit is dead above MI.
|
|
|
|
RegUnits.erase(I);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Now we know the height of MI. Update any regunits read.
|
|
|
|
for (unsigned i = 0, e = ReadOps.size(); i != e; ++i) {
|
|
|
|
unsigned Reg = MI->getOperand(ReadOps[i]).getReg();
|
|
|
|
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
|
|
|
|
LiveRegUnit &LRU = RegUnits[*Units];
|
|
|
|
// Set the height to the highest reader of the unit.
|
|
|
|
if (LRU.Cycle <= Height && LRU.MI != MI) {
|
|
|
|
LRU.Cycle = Height;
|
|
|
|
LRU.MI = MI;
|
|
|
|
LRU.Op = ReadOps[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return Height;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
typedef DenseMap<const MachineInstr *, unsigned> MIHeightMap;
|
|
|
|
|
|
|
|
// Push the height of DefMI upwards if required to match UseMI.
|
|
|
|
// Return true if this is the first time DefMI was seen.
|
|
|
|
static bool pushDepHeight(const DataDep &Dep,
|
|
|
|
const MachineInstr *UseMI, unsigned UseHeight,
|
|
|
|
MIHeightMap &Heights,
|
2012-10-05 01:30:40 +08:00
|
|
|
const TargetSchedModel &SchedModel,
|
2012-08-02 06:36:00 +08:00
|
|
|
const TargetInstrInfo *TII) {
|
|
|
|
// Adjust height by Dep.DefMI latency.
|
|
|
|
if (!Dep.DefMI->isTransient())
|
2012-10-05 01:30:40 +08:00
|
|
|
UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp,
|
2013-06-15 12:49:57 +08:00
|
|
|
UseMI, Dep.UseOp);
|
2012-08-02 06:36:00 +08:00
|
|
|
|
|
|
|
// Update Heights[DefMI] to be the maximum height seen.
|
|
|
|
MIHeightMap::iterator I;
|
|
|
|
bool New;
|
2014-03-02 21:30:33 +08:00
|
|
|
std::tie(I, New) = Heights.insert(std::make_pair(Dep.DefMI, UseHeight));
|
2012-08-02 06:36:00 +08:00
|
|
|
if (New)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// DefMI has been pushed before. Give it the max height.
|
|
|
|
if (I->second < UseHeight)
|
|
|
|
I->second = UseHeight;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-10-12 00:46:07 +08:00
|
|
|
/// Assuming that the virtual register defined by DefMI:DefOp was used by
|
|
|
|
/// Trace.back(), add it to the live-in lists of all the blocks in Trace. Stop
|
|
|
|
/// when reaching the block that contains DefMI.
|
2012-08-02 06:36:00 +08:00
|
|
|
void MachineTraceMetrics::Ensemble::
|
2012-10-12 00:46:07 +08:00
|
|
|
addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
|
2012-08-02 06:36:00 +08:00
|
|
|
ArrayRef<const MachineBasicBlock*> Trace) {
|
|
|
|
assert(!Trace.empty() && "Trace should contain at least one block");
|
2012-10-12 00:46:07 +08:00
|
|
|
unsigned Reg = DefMI->getOperand(DefOp).getReg();
|
2012-08-02 06:36:00 +08:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(Reg));
|
|
|
|
const MachineBasicBlock *DefMBB = DefMI->getParent();
|
|
|
|
|
|
|
|
// Reg is live-in to all blocks in Trace that follow DefMBB.
|
|
|
|
for (unsigned i = Trace.size(); i; --i) {
|
|
|
|
const MachineBasicBlock *MBB = Trace[i-1];
|
|
|
|
if (MBB == DefMBB)
|
|
|
|
return;
|
|
|
|
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
|
|
|
|
// Just add the register. The height will be updated later.
|
|
|
|
TBI.LiveIns.push_back(Reg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Compute instruction heights in the trace through MBB. This updates MBB and
|
|
|
|
/// the blocks below it in the trace. It is assumed that the trace has already
|
|
|
|
/// been computed.
|
|
|
|
void MachineTraceMetrics::Ensemble::
|
|
|
|
computeInstrHeights(const MachineBasicBlock *MBB) {
|
|
|
|
// The bottom of the trace may already be computed.
|
|
|
|
// Find the blocks that need updating.
|
|
|
|
SmallVector<const MachineBasicBlock*, 8> Stack;
|
|
|
|
do {
|
|
|
|
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
|
|
|
|
assert(TBI.hasValidHeight() && "Incomplete trace");
|
|
|
|
if (TBI.HasValidInstrHeights)
|
|
|
|
break;
|
|
|
|
Stack.push_back(MBB);
|
|
|
|
TBI.LiveIns.clear();
|
|
|
|
MBB = TBI.Succ;
|
|
|
|
} while (MBB);
|
|
|
|
|
|
|
|
// As we move upwards in the trace, keep track of instructions that are
|
|
|
|
// required by deeper trace instructions. Map MI -> height required so far.
|
|
|
|
MIHeightMap Heights;
|
|
|
|
|
|
|
|
// For physregs, the def isn't known when we see the use.
|
|
|
|
// Instead, keep track of the highest use of each regunit.
|
|
|
|
SparseSet<LiveRegUnit> RegUnits;
|
|
|
|
RegUnits.setUniverse(MTM.TRI->getNumRegUnits());
|
|
|
|
|
|
|
|
// If the bottom of the trace was already precomputed, initialize heights
|
|
|
|
// from its live-in list.
|
|
|
|
// MBB is the highest precomputed block in the trace.
|
|
|
|
if (MBB) {
|
|
|
|
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
|
2015-07-07 00:19:14 +08:00
|
|
|
for (LiveInReg &LI : TBI.LiveIns) {
|
2012-08-02 06:36:00 +08:00
|
|
|
if (TargetRegisterInfo::isVirtualRegister(LI.Reg)) {
|
|
|
|
// For virtual registers, the def latency is included.
|
|
|
|
unsigned &Height = Heights[MTM.MRI->getVRegDef(LI.Reg)];
|
|
|
|
if (Height < LI.Height)
|
|
|
|
Height = LI.Height;
|
|
|
|
} else {
|
|
|
|
// For register units, the def latency is not included because we don't
|
|
|
|
// know the def yet.
|
|
|
|
RegUnits[LI.Reg].Cycle = LI.Height;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Go through the trace blocks in bottom-up order.
|
|
|
|
SmallVector<DataDep, 8> Deps;
|
|
|
|
for (;!Stack.empty(); Stack.pop_back()) {
|
|
|
|
MBB = Stack.back();
|
|
|
|
DEBUG(dbgs() << "Heights for BB#" << MBB->getNumber() << ":\n");
|
|
|
|
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
|
|
|
|
TBI.HasValidInstrHeights = true;
|
2012-08-03 02:45:54 +08:00
|
|
|
TBI.CriticalPath = 0;
|
2012-08-02 06:36:00 +08:00
|
|
|
|
2013-04-03 01:49:51 +08:00
|
|
|
DEBUG({
|
|
|
|
dbgs() << format("%7u Instructions\n", TBI.InstrHeight);
|
|
|
|
ArrayRef<unsigned> PRHeights = getProcResourceHeights(MBB->getNumber());
|
|
|
|
for (unsigned K = 0; K != PRHeights.size(); ++K)
|
|
|
|
if (PRHeights[K]) {
|
|
|
|
unsigned Factor = MTM.SchedModel.getResourceFactor(K);
|
|
|
|
dbgs() << format("%6uc @ ", MTM.getCycles(PRHeights[K]))
|
|
|
|
<< MTM.SchedModel.getProcResource(K)->Name << " ("
|
|
|
|
<< PRHeights[K]/Factor << " ops x" << Factor << ")\n";
|
|
|
|
}
|
|
|
|
});
|
|
|
|
|
2012-08-02 06:36:00 +08:00
|
|
|
// Get dependencies from PHIs in the trace successor.
|
2012-08-11 04:11:38 +08:00
|
|
|
const MachineBasicBlock *Succ = TBI.Succ;
|
|
|
|
// If MBB is the last block in the trace, and it has a back-edge to the
|
|
|
|
// loop header, get loop-carried dependencies from PHIs in the header. For
|
|
|
|
// that purpose, pretend that all the loop header PHIs have height 0.
|
|
|
|
if (!Succ)
|
|
|
|
if (const MachineLoop *Loop = getLoopFor(MBB))
|
|
|
|
if (MBB->isSuccessor(Loop->getHeader()))
|
|
|
|
Succ = Loop->getHeader();
|
|
|
|
|
|
|
|
if (Succ) {
|
2014-05-01 06:17:38 +08:00
|
|
|
for (const auto &PHI : *Succ) {
|
|
|
|
if (!PHI.isPHI())
|
|
|
|
break;
|
2012-08-02 06:36:00 +08:00
|
|
|
Deps.clear();
|
2014-05-01 06:17:38 +08:00
|
|
|
getPHIDeps(&PHI, Deps, MBB, MTM.MRI);
|
2012-08-11 04:11:38 +08:00
|
|
|
if (!Deps.empty()) {
|
|
|
|
// Loop header PHI heights are all 0.
|
2014-05-01 06:17:38 +08:00
|
|
|
unsigned Height = TBI.Succ ? Cycles.lookup(&PHI).Height : 0;
|
|
|
|
DEBUG(dbgs() << "pred\t" << Height << '\t' << PHI);
|
|
|
|
if (pushDepHeight(Deps.front(), &PHI, Height,
|
2012-10-05 01:30:40 +08:00
|
|
|
Heights, MTM.SchedModel, MTM.TII))
|
2012-10-12 00:46:07 +08:00
|
|
|
addLiveIns(Deps.front().DefMI, Deps.front().DefOp, Stack);
|
2012-08-11 04:11:38 +08:00
|
|
|
}
|
2012-08-02 06:36:00 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Go through the block backwards.
|
|
|
|
for (MachineBasicBlock::const_iterator BI = MBB->end(), BB = MBB->begin();
|
|
|
|
BI != BB;) {
|
|
|
|
const MachineInstr *MI = --BI;
|
|
|
|
|
|
|
|
// Find the MI height as determined by virtual register uses in the
|
|
|
|
// trace below.
|
|
|
|
unsigned Cycle = 0;
|
|
|
|
MIHeightMap::iterator HeightI = Heights.find(MI);
|
|
|
|
if (HeightI != Heights.end()) {
|
|
|
|
Cycle = HeightI->second;
|
|
|
|
// We won't be seeing any more MI uses.
|
|
|
|
Heights.erase(HeightI);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Don't process PHI deps. They depend on the specific predecessor, and
|
|
|
|
// we'll get them when visiting the predecessor.
|
|
|
|
Deps.clear();
|
|
|
|
bool HasPhysRegs = !MI->isPHI() && getDataDeps(MI, Deps, MTM.MRI);
|
|
|
|
|
|
|
|
// There may also be regunit dependencies to include in the height.
|
|
|
|
if (HasPhysRegs)
|
|
|
|
Cycle = updatePhysDepsUpwards(MI, Cycle, RegUnits,
|
2012-10-05 01:30:40 +08:00
|
|
|
MTM.SchedModel, MTM.TII, MTM.TRI);
|
2012-08-02 06:36:00 +08:00
|
|
|
|
|
|
|
// Update the required height of any virtual registers read by MI.
|
2015-07-01 00:30:22 +08:00
|
|
|
for (const DataDep &Dep : Deps)
|
|
|
|
if (pushDepHeight(Dep, MI, Cycle, Heights, MTM.SchedModel, MTM.TII))
|
|
|
|
addLiveIns(Dep.DefMI, Dep.DefOp, Stack);
|
2012-08-03 02:45:54 +08:00
|
|
|
|
|
|
|
InstrCycles &MICycles = Cycles[MI];
|
|
|
|
MICycles.Height = Cycle;
|
|
|
|
if (!TBI.HasValidInstrDepths) {
|
|
|
|
DEBUG(dbgs() << Cycle << '\t' << *MI);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
// Update critical path length.
|
|
|
|
TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Depth);
|
|
|
|
DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << *MI);
|
2012-08-02 06:36:00 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Update virtual live-in heights. They were added by addLiveIns() with a 0
|
|
|
|
// height because the final height isn't known until now.
|
|
|
|
DEBUG(dbgs() << "BB#" << MBB->getNumber() << " Live-ins:");
|
2015-07-01 00:30:22 +08:00
|
|
|
for (LiveInReg &LIR : TBI.LiveIns) {
|
2012-08-02 06:36:00 +08:00
|
|
|
const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
|
|
|
|
LIR.Height = Heights.lookup(DefMI);
|
|
|
|
DEBUG(dbgs() << ' ' << PrintReg(LIR.Reg) << '@' << LIR.Height);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Transfer the live regunits to the live-in list.
|
|
|
|
for (SparseSet<LiveRegUnit>::const_iterator
|
|
|
|
RI = RegUnits.begin(), RE = RegUnits.end(); RI != RE; ++RI) {
|
|
|
|
TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle));
|
|
|
|
DEBUG(dbgs() << ' ' << PrintRegUnit(RI->RegUnit, MTM.TRI)
|
|
|
|
<< '@' << RI->Cycle);
|
|
|
|
}
|
|
|
|
DEBUG(dbgs() << '\n');
|
2012-08-03 02:45:54 +08:00
|
|
|
|
|
|
|
if (!TBI.HasValidInstrDepths)
|
|
|
|
continue;
|
|
|
|
// Add live-ins to the critical path length.
|
|
|
|
TBI.CriticalPath = std::max(TBI.CriticalPath,
|
|
|
|
computeCrossBlockCriticalPath(TBI));
|
|
|
|
DEBUG(dbgs() << "Critical path: " << TBI.CriticalPath << '\n');
|
2012-08-02 06:36:00 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-07-27 02:38:11 +08:00
|
|
|
MachineTraceMetrics::Trace
|
|
|
|
MachineTraceMetrics::Ensemble::getTrace(const MachineBasicBlock *MBB) {
|
2015-07-04 23:00:28 +08:00
|
|
|
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
|
|
|
|
|
|
|
|
if (!TBI.hasValidDepth() || !TBI.hasValidHeight())
|
|
|
|
computeTrace(MBB);
|
|
|
|
if (!TBI.HasValidInstrDepths)
|
|
|
|
computeInstrDepths(MBB);
|
|
|
|
if (!TBI.HasValidInstrHeights)
|
|
|
|
computeInstrHeights(MBB);
|
|
|
|
|
|
|
|
return Trace(*this, TBI);
|
2012-07-27 02:38:11 +08:00
|
|
|
}
|
|
|
|
|
2012-08-08 02:02:19 +08:00
|
|
|
unsigned
|
|
|
|
MachineTraceMetrics::Trace::getInstrSlack(const MachineInstr *MI) const {
|
|
|
|
assert(MI && "Not an instruction.");
|
|
|
|
assert(getBlockNum() == unsigned(MI->getParent()->getNumber()) &&
|
|
|
|
"MI must be in the trace center block");
|
|
|
|
InstrCycles Cyc = getInstrCycles(MI);
|
|
|
|
return getCriticalPath() - (Cyc.Depth + Cyc.Height);
|
|
|
|
}
|
|
|
|
|
2012-08-11 06:27:27 +08:00
|
|
|
unsigned
|
|
|
|
MachineTraceMetrics::Trace::getPHIDepth(const MachineInstr *PHI) const {
|
|
|
|
const MachineBasicBlock *MBB = TE.MTM.MF->getBlockNumbered(getBlockNum());
|
|
|
|
SmallVector<DataDep, 1> Deps;
|
|
|
|
getPHIDeps(PHI, Deps, MBB, TE.MTM.MRI);
|
|
|
|
assert(Deps.size() == 1 && "PHI doesn't have MBB as a predecessor");
|
|
|
|
DataDep &Dep = Deps.front();
|
|
|
|
unsigned DepCycle = getInstrCycles(Dep.DefMI).Depth;
|
|
|
|
// Add latency if DefMI is a real instruction. Transients get latency 0.
|
|
|
|
if (!Dep.DefMI->isTransient())
|
2012-10-05 01:30:40 +08:00
|
|
|
DepCycle += TE.MTM.SchedModel
|
2013-06-15 12:49:57 +08:00
|
|
|
.computeOperandLatency(Dep.DefMI, Dep.DefOp, PHI, Dep.UseOp);
|
2012-08-11 06:27:27 +08:00
|
|
|
return DepCycle;
|
|
|
|
}
|
|
|
|
|
2014-08-04 05:35:39 +08:00
|
|
|
/// When bottom is set include instructions in current block in estimate.
|
2012-08-08 02:02:19 +08:00
|
|
|
unsigned MachineTraceMetrics::Trace::getResourceDepth(bool Bottom) const {
|
2013-04-03 01:49:51 +08:00
|
|
|
// Find the limiting processor resource.
|
|
|
|
// Numbers have been pre-scaled to be comparable.
|
|
|
|
unsigned PRMax = 0;
|
|
|
|
ArrayRef<unsigned> PRDepths = TE.getProcResourceDepths(getBlockNum());
|
|
|
|
if (Bottom) {
|
|
|
|
ArrayRef<unsigned> PRCycles = TE.MTM.getProcResourceCycles(getBlockNum());
|
|
|
|
for (unsigned K = 0; K != PRDepths.size(); ++K)
|
|
|
|
PRMax = std::max(PRMax, PRDepths[K] + PRCycles[K]);
|
|
|
|
} else {
|
|
|
|
for (unsigned K = 0; K != PRDepths.size(); ++K)
|
|
|
|
PRMax = std::max(PRMax, PRDepths[K]);
|
|
|
|
}
|
|
|
|
// Convert to cycle count.
|
|
|
|
PRMax = TE.MTM.getCycles(PRMax);
|
|
|
|
|
2014-08-04 05:35:39 +08:00
|
|
|
/// All instructions before current block
|
2012-08-08 02:02:19 +08:00
|
|
|
unsigned Instrs = TBI.InstrDepth;
|
2014-08-04 05:35:39 +08:00
|
|
|
// plus instructions in current block
|
2012-08-08 02:02:19 +08:00
|
|
|
if (Bottom)
|
|
|
|
Instrs += TE.MTM.BlockInfo[getBlockNum()].InstrCount;
|
2012-10-05 01:30:40 +08:00
|
|
|
if (unsigned IW = TE.MTM.SchedModel.getIssueWidth())
|
|
|
|
Instrs /= IW;
|
2012-08-11 06:27:27 +08:00
|
|
|
// Assume issue width 1 without a schedule model.
|
2013-04-03 01:49:51 +08:00
|
|
|
return std::max(Instrs, PRMax);
|
2012-08-11 06:27:27 +08:00
|
|
|
}
|
|
|
|
|
2014-08-04 05:35:39 +08:00
|
|
|
unsigned MachineTraceMetrics::Trace::getResourceLength(
|
|
|
|
ArrayRef<const MachineBasicBlock *> Extrablocks,
|
|
|
|
ArrayRef<const MCSchedClassDesc *> ExtraInstrs,
|
|
|
|
ArrayRef<const MCSchedClassDesc *> RemoveInstrs) const {
|
2013-04-03 01:49:51 +08:00
|
|
|
// Add up resources above and below the center block.
|
|
|
|
ArrayRef<unsigned> PRDepths = TE.getProcResourceDepths(getBlockNum());
|
|
|
|
ArrayRef<unsigned> PRHeights = TE.getProcResourceHeights(getBlockNum());
|
|
|
|
unsigned PRMax = 0;
|
2014-08-04 05:35:39 +08:00
|
|
|
|
|
|
|
// Capture computing cycles from extra instructions
|
|
|
|
auto extraCycles = [this](ArrayRef<const MCSchedClassDesc *> Instrs,
|
|
|
|
unsigned ResourceIdx)
|
|
|
|
->unsigned {
|
|
|
|
unsigned Cycles = 0;
|
2015-07-07 00:19:14 +08:00
|
|
|
for (const MCSchedClassDesc *SC : Instrs) {
|
2013-04-27 11:54:20 +08:00
|
|
|
if (!SC->isValid())
|
|
|
|
continue;
|
|
|
|
for (TargetSchedModel::ProcResIter
|
2014-08-04 05:35:39 +08:00
|
|
|
PI = TE.MTM.SchedModel.getWriteProcResBegin(SC),
|
|
|
|
PE = TE.MTM.SchedModel.getWriteProcResEnd(SC);
|
|
|
|
PI != PE; ++PI) {
|
|
|
|
if (PI->ProcResourceIdx != ResourceIdx)
|
2013-04-27 11:54:20 +08:00
|
|
|
continue;
|
2014-08-04 05:35:39 +08:00
|
|
|
Cycles +=
|
|
|
|
(PI->Cycles * TE.MTM.SchedModel.getResourceFactor(ResourceIdx));
|
2013-04-27 11:54:20 +08:00
|
|
|
}
|
|
|
|
}
|
2014-08-04 05:35:39 +08:00
|
|
|
return Cycles;
|
|
|
|
};
|
|
|
|
|
|
|
|
for (unsigned K = 0; K != PRDepths.size(); ++K) {
|
|
|
|
unsigned PRCycles = PRDepths[K] + PRHeights[K];
|
2015-07-07 00:19:14 +08:00
|
|
|
for (const MachineBasicBlock *MBB : Extrablocks)
|
|
|
|
PRCycles += TE.MTM.getProcResourceCycles(MBB->getNumber())[K];
|
2014-08-04 05:35:39 +08:00
|
|
|
PRCycles += extraCycles(ExtraInstrs, K);
|
|
|
|
PRCycles -= extraCycles(RemoveInstrs, K);
|
2013-04-03 01:49:51 +08:00
|
|
|
PRMax = std::max(PRMax, PRCycles);
|
|
|
|
}
|
|
|
|
// Convert to cycle count.
|
|
|
|
PRMax = TE.MTM.getCycles(PRMax);
|
|
|
|
|
2014-08-04 05:35:39 +08:00
|
|
|
// Instrs: #instructions in current trace outside current block.
|
2012-08-11 06:27:27 +08:00
|
|
|
unsigned Instrs = TBI.InstrDepth + TBI.InstrHeight;
|
2014-08-04 05:35:39 +08:00
|
|
|
// Add instruction count from the extra blocks.
|
2015-07-07 00:19:14 +08:00
|
|
|
for (const MachineBasicBlock *MBB : Extrablocks)
|
|
|
|
Instrs += TE.MTM.getResources(MBB)->InstrCount;
|
2014-08-04 05:35:39 +08:00
|
|
|
Instrs += ExtraInstrs.size();
|
|
|
|
Instrs -= RemoveInstrs.size();
|
2012-10-05 01:30:40 +08:00
|
|
|
if (unsigned IW = TE.MTM.SchedModel.getIssueWidth())
|
|
|
|
Instrs /= IW;
|
2012-08-08 02:02:19 +08:00
|
|
|
// Assume issue width 1 without a schedule model.
|
2013-04-03 01:49:51 +08:00
|
|
|
return std::max(Instrs, PRMax);
|
2012-08-08 02:02:19 +08:00
|
|
|
}
|
|
|
|
|
2014-08-04 05:35:39 +08:00
|
|
|
bool MachineTraceMetrics::Trace::isDepInTrace(const MachineInstr *DefMI,
|
|
|
|
const MachineInstr *UseMI) const {
|
|
|
|
if (DefMI->getParent() == UseMI->getParent())
|
|
|
|
return true;
|
|
|
|
|
|
|
|
const TraceBlockInfo &DepTBI = TE.BlockInfo[DefMI->getParent()->getNumber()];
|
|
|
|
const TraceBlockInfo &TBI = TE.BlockInfo[UseMI->getParent()->getNumber()];
|
|
|
|
|
|
|
|
return DepTBI.isUsefulDominator(TBI);
|
|
|
|
}
|
|
|
|
|
2012-07-28 07:58:38 +08:00
|
|
|
void MachineTraceMetrics::Ensemble::print(raw_ostream &OS) const {
|
|
|
|
OS << getName() << " ensemble:\n";
|
|
|
|
for (unsigned i = 0, e = BlockInfo.size(); i != e; ++i) {
|
|
|
|
OS << " BB#" << i << '\t';
|
|
|
|
BlockInfo[i].print(OS);
|
|
|
|
OS << '\n';
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineTraceMetrics::TraceBlockInfo::print(raw_ostream &OS) const {
|
|
|
|
if (hasValidDepth()) {
|
|
|
|
OS << "depth=" << InstrDepth;
|
|
|
|
if (Pred)
|
|
|
|
OS << " pred=BB#" << Pred->getNumber();
|
|
|
|
else
|
|
|
|
OS << " pred=null";
|
|
|
|
OS << " head=BB#" << Head;
|
2012-08-01 04:44:38 +08:00
|
|
|
if (HasValidInstrDepths)
|
|
|
|
OS << " +instrs";
|
2012-07-28 07:58:38 +08:00
|
|
|
} else
|
|
|
|
OS << "depth invalid";
|
|
|
|
OS << ", ";
|
|
|
|
if (hasValidHeight()) {
|
|
|
|
OS << "height=" << InstrHeight;
|
|
|
|
if (Succ)
|
|
|
|
OS << " succ=BB#" << Succ->getNumber();
|
|
|
|
else
|
|
|
|
OS << " succ=null";
|
|
|
|
OS << " tail=BB#" << Tail;
|
2012-08-01 04:44:38 +08:00
|
|
|
if (HasValidInstrHeights)
|
|
|
|
OS << " +instrs";
|
2012-07-28 07:58:38 +08:00
|
|
|
} else
|
|
|
|
OS << "height invalid";
|
2012-08-03 02:45:54 +08:00
|
|
|
if (HasValidInstrDepths && HasValidInstrHeights)
|
|
|
|
OS << ", crit=" << CriticalPath;
|
2012-07-28 07:58:38 +08:00
|
|
|
}
|
|
|
|
|
2012-07-27 02:38:11 +08:00
|
|
|
void MachineTraceMetrics::Trace::print(raw_ostream &OS) const {
|
2012-07-28 07:58:36 +08:00
|
|
|
unsigned MBBNum = &TBI - &TE.BlockInfo[0];
|
|
|
|
|
|
|
|
OS << TE.getName() << " trace BB#" << TBI.Head << " --> BB#" << MBBNum
|
|
|
|
<< " --> BB#" << TBI.Tail << ':';
|
2012-07-27 02:38:11 +08:00
|
|
|
if (TBI.hasValidHeight() && TBI.hasValidDepth())
|
|
|
|
OS << ' ' << getInstrCount() << " instrs.";
|
2012-08-03 02:45:54 +08:00
|
|
|
if (TBI.HasValidInstrDepths && TBI.HasValidInstrHeights)
|
|
|
|
OS << ' ' << TBI.CriticalPath << " cycles.";
|
2012-07-27 02:38:11 +08:00
|
|
|
|
|
|
|
const MachineTraceMetrics::TraceBlockInfo *Block = &TBI;
|
2012-07-28 07:58:36 +08:00
|
|
|
OS << "\nBB#" << MBBNum;
|
2012-07-27 02:38:11 +08:00
|
|
|
while (Block->hasValidDepth() && Block->Pred) {
|
|
|
|
unsigned Num = Block->Pred->getNumber();
|
|
|
|
OS << " <- BB#" << Num;
|
|
|
|
Block = &TE.BlockInfo[Num];
|
|
|
|
}
|
|
|
|
|
|
|
|
Block = &TBI;
|
2012-07-28 07:58:36 +08:00
|
|
|
OS << "\n ";
|
2012-07-27 02:38:11 +08:00
|
|
|
while (Block->hasValidHeight() && Block->Succ) {
|
|
|
|
unsigned Num = Block->Succ->getNumber();
|
|
|
|
OS << " -> BB#" << Num;
|
|
|
|
Block = &TE.BlockInfo[Num];
|
|
|
|
}
|
|
|
|
OS << '\n';
|
|
|
|
}
|