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llvm-project/llvm/test/CodeGen/X86/atomic-load-store-wide.ll

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X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
; RUN: llc < %s -mcpu=corei7 -march=x86 -verify-machineinstrs | FileCheck %s
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually. llvm-svn: 138505
2011-08-25 06:33:28 +08:00
; 64-bit load/store on x86-32
; FIXME: The generated code can be substantially improved.
define void @test1(i64* %ptr, i64 %val1) {
; CHECK: test1
; CHECK: cmpxchg8b
; CHECK-NEXT: jne
Error out on CodeGen of unaligned load/store. Fix test so it isn't accidentally testing that case. llvm-svn: 139641
2011-09-14 04:50:54 +08:00
store atomic i64 %val1, i64* %ptr seq_cst, align 8
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually. llvm-svn: 138505
2011-08-25 06:33:28 +08:00
ret void
}
define i64 @test2(i64* %ptr) {
; CHECK: test2
; CHECK: cmpxchg8b
Error out on CodeGen of unaligned load/store. Fix test so it isn't accidentally testing that case. llvm-svn: 139641
2011-09-14 04:50:54 +08:00
%val = load atomic i64* %ptr seq_cst, align 8
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually. llvm-svn: 138505
2011-08-25 06:33:28 +08:00
ret i64 %val
}