[RISCV] Support and tests for a variety of additional LLVM IR constructs
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
llvm-svn: 318737
2017-11-21 16:11:03 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; Basic shift support is tested as part of ALU.ll. This file ensures that
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; shifts which may not be supported natively are lowered properly.
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define i64 @lshr64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: lshr64:
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2017-12-05 01:18:51 +08:00
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; RV32I: # %bb.0:
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2017-12-11 19:53:54 +08:00
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; RV32I-NEXT: sw ra, 12(sp)
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[RISCV] Support and tests for a variety of additional LLVM IR constructs
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
llvm-svn: 318737
2017-11-21 16:11:03 +08:00
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; RV32I-NEXT: lui a3, %hi(__lshrdi3)
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; RV32I-NEXT: addi a3, a3, %lo(__lshrdi3)
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; RV32I-NEXT: jalr ra, a3, 0
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2017-12-11 19:53:54 +08:00
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; RV32I-NEXT: lw ra, 12(sp)
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[RISCV] Support and tests for a variety of additional LLVM IR constructs
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
llvm-svn: 318737
2017-11-21 16:11:03 +08:00
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = lshr i64 %a, %b
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ret i64 %1
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}
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define i64 @ashr64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: ashr64:
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2017-12-05 01:18:51 +08:00
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; RV32I: # %bb.0:
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2017-12-11 19:53:54 +08:00
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; RV32I-NEXT: sw ra, 12(sp)
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[RISCV] Support and tests for a variety of additional LLVM IR constructs
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
llvm-svn: 318737
2017-11-21 16:11:03 +08:00
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; RV32I-NEXT: lui a3, %hi(__ashrdi3)
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; RV32I-NEXT: addi a3, a3, %lo(__ashrdi3)
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; RV32I-NEXT: jalr ra, a3, 0
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2017-12-11 19:53:54 +08:00
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; RV32I-NEXT: lw ra, 12(sp)
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[RISCV] Support and tests for a variety of additional LLVM IR constructs
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
llvm-svn: 318737
2017-11-21 16:11:03 +08:00
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = ashr i64 %a, %b
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ret i64 %1
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}
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define i64 @shl64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: shl64:
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2017-12-05 01:18:51 +08:00
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; RV32I: # %bb.0:
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2017-12-11 19:53:54 +08:00
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; RV32I-NEXT: sw ra, 12(sp)
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[RISCV] Support and tests for a variety of additional LLVM IR constructs
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
llvm-svn: 318737
2017-11-21 16:11:03 +08:00
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; RV32I-NEXT: lui a3, %hi(__ashldi3)
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; RV32I-NEXT: addi a3, a3, %lo(__ashldi3)
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; RV32I-NEXT: jalr ra, a3, 0
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2017-12-11 19:53:54 +08:00
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; RV32I-NEXT: lw ra, 12(sp)
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[RISCV] Support and tests for a variety of additional LLVM IR constructs
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
llvm-svn: 318737
2017-11-21 16:11:03 +08:00
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = shl i64 %a, %b
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ret i64 %1
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}
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