2015-02-02 00:15:07 +08:00
|
|
|
set(LLVM_TARGET_DEFINITIONS X86.td)
|
|
|
|
|
|
2018-04-04 20:37:44 +08:00
|
|
|
tablegen(LLVM X86GenAsmMatcher.inc -gen-asm-matcher)
|
2015-02-02 00:15:07 +08:00
|
|
|
tablegen(LLVM X86GenAsmWriter.inc -gen-asm-writer)
|
|
|
|
|
tablegen(LLVM X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
|
|
|
|
|
tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)
|
2018-04-04 20:37:44 +08:00
|
|
|
tablegen(LLVM X86GenDAGISel.inc -gen-dag-isel)
|
|
|
|
|
tablegen(LLVM X86GenDisassemblerTables.inc -gen-disassembler)
|
2017-03-07 16:11:19 +08:00
|
|
|
tablegen(LLVM X86GenEVEX2VEXTables.inc -gen-x86-EVEX2VEX-tables)
|
2018-04-04 20:37:44 +08:00
|
|
|
tablegen(LLVM X86GenFastISel.inc -gen-fast-isel)
|
2017-08-04 05:52:25 +08:00
|
|
|
tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)
|
2018-04-04 20:37:44 +08:00
|
|
|
tablegen(LLVM X86GenInstrInfo.inc -gen-instr-info)
|
|
|
|
|
tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)
|
|
|
|
|
tablegen(LLVM X86GenRegisterInfo.inc -gen-register-info)
|
|
|
|
|
tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)
|
2017-02-10 15:05:56 +08:00
|
|
|
|
2018-01-08 05:03:43 +08:00
|
|
|
if (X86_GEN_FOLD_TABLES)
|
|
|
|
|
tablegen(LLVM X86GenFoldTables.inc -gen-x86-fold-tables)
|
|
|
|
|
endif()
|
2017-10-08 17:20:32 +08:00
|
|
|
|
2015-02-02 00:15:07 +08:00
|
|
|
add_public_tablegen_target(X86CommonTableGen)
|
|
|
|
|
|
|
|
|
|
set(sources
|
2018-04-04 09:21:16 +08:00
|
|
|
ShadowCallStack.cpp
|
2015-02-02 00:15:07 +08:00
|
|
|
X86AsmPrinter.cpp
|
2015-02-02 00:56:04 +08:00
|
|
|
X86CallFrameOptimization.cpp
|
2018-01-09 16:51:18 +08:00
|
|
|
X86CallingConv.cpp
|
2017-08-04 05:52:25 +08:00
|
|
|
X86CallLowering.cpp
|
2017-07-17 01:39:56 +08:00
|
|
|
X86CmovConversion.cpp
|
2017-10-22 19:43:08 +08:00
|
|
|
X86DomainReassignment.cpp
|
2015-05-23 02:10:47 +08:00
|
|
|
X86ExpandPseudo.cpp
|
2015-02-02 00:15:07 +08:00
|
|
|
X86FastISel.cpp
|
2016-06-29 01:11:15 +08:00
|
|
|
X86FixupBWInsts.cpp
|
|
|
|
|
X86FixupLEAs.cpp
|
2018-04-02 21:48:28 +08:00
|
|
|
X86AvoidStoreForwardingBlocks.cpp
|
2016-07-08 06:50:23 +08:00
|
|
|
X86FixupSetCC.cpp
|
[x86] Introduce a pass to begin more systematically fixing PR36028 and similar issues.
The key idea is to lower COPY nodes populating EFLAGS by scanning the
uses of EFLAGS and introducing dedicated code to preserve the necessary
state in a GPR. In the vast majority of cases, these uses are cmovCC and
jCC instructions. For such cases, we can very easily save and restore
the necessary information by simply inserting a setCC into a GPR where
the original flags are live, and then testing that GPR directly to feed
the cmov or conditional branch.
However, things are a bit more tricky if arithmetic is using the flags.
This patch handles the vast majority of cases that seem to come up in
practice: adc, adcx, adox, rcl, and rcr; all without taking advantage of
partially preserved EFLAGS as LLVM doesn't currently model that at all.
There are a large number of operations that techinaclly observe EFLAGS
currently but shouldn't in this case -- they typically are using DF.
Currently, they will not be handled by this approach. However, I have
never seen this issue come up in practice. It is already pretty rare to
have these patterns come up in practical code with LLVM. I had to resort
to writing MIR tests to cover most of the logic in this pass already.
I suspect even with its current amount of coverage of arithmetic users
of EFLAGS it will be a significant improvement over the current use of
pushf/popf. It will also produce substantially faster code in most of
the common patterns.
This patch also removes all of the old lowering for EFLAGS copies, and
the hack that forced us to use a frame pointer when EFLAGS copies were
found anywhere in a function so that the dynamic stack adjustment wasn't
a problem. None of this is needed as we now lower all of these copies
directly in MI and without require stack adjustments.
Lots of thanks to Reid who came up with several aspects of this
approach, and Craig who helped me work out a couple of things tripping
me up while working on this.
Differential Revision: https://reviews.llvm.org/D45146
llvm-svn: 329657
2018-04-10 09:41:17 +08:00
|
|
|
X86FlagsCopyLowering.cpp
|
2015-02-02 00:15:07 +08:00
|
|
|
X86FloatingPoint.cpp
|
|
|
|
|
X86FrameLowering.cpp
|
2017-08-04 05:52:25 +08:00
|
|
|
X86InstructionSelector.cpp
|
2015-02-02 00:15:07 +08:00
|
|
|
X86ISelDAGToDAG.cpp
|
|
|
|
|
X86ISelLowering.cpp
|
2018-01-09 16:51:18 +08:00
|
|
|
X86IndirectBranchTracking.cpp
|
2016-10-15 02:20:41 +08:00
|
|
|
X86InterleavedAccess.cpp
|
2016-08-12 06:07:33 +08:00
|
|
|
X86InstrFMA3Info.cpp
|
2015-02-02 00:15:07 +08:00
|
|
|
X86InstrInfo.cpp
|
2016-12-28 18:12:48 +08:00
|
|
|
X86EvexToVex.cpp
|
2017-08-04 05:52:25 +08:00
|
|
|
X86LegalizerInfo.cpp
|
2015-02-02 00:15:07 +08:00
|
|
|
X86MCInstLower.cpp
|
|
|
|
|
X86MachineFunctionInfo.cpp
|
2017-02-01 10:54:34 +08:00
|
|
|
X86MacroFusion.cpp
|
2016-06-29 01:11:15 +08:00
|
|
|
X86OptimizeLEAs.cpp
|
2015-02-02 00:15:07 +08:00
|
|
|
X86PadShortFunction.cpp
|
2017-08-04 05:52:25 +08:00
|
|
|
X86RegisterBankInfo.cpp
|
2015-02-02 00:15:07 +08:00
|
|
|
X86RegisterInfo.cpp
|
Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..
Summary:
First, we need to explain the core of the vulnerability. Note that this
is a very incomplete description, please see the Project Zero blog post
for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html
The basis for branch target injection is to direct speculative execution
of the processor to some "gadget" of executable code by poisoning the
prediction of indirect branches with the address of that gadget. The
gadget in turn contains an operation that provides a side channel for
reading data. Most commonly, this will look like a load of secret data
followed by a branch on the loaded value and then a load of some
predictable cache line. The attacker then uses timing of the processors
cache to determine which direction the branch took *in the speculative
execution*, and in turn what one bit of the loaded value was. Due to the
nature of these timing side channels and the branch predictor on Intel
processors, this allows an attacker to leak data only accessible to
a privileged domain (like the kernel) back into an unprivileged domain.
The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In many
cases, the compiler can simply use directed conditional branches and
a small search tree. LLVM already has support for lowering switches in
this way and the first step of this patch is to disable jump-table
lowering of switches and introduce a pass to rewrite explicit indirectbr
sequences into a switch over integers.
However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as
a trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures the
processor predicts the return to go to a controlled, known location. The
retpoline then "smashes" the return address pushed onto the stack by the
call with the desired target of the original indirect call. The result
is a predicted return to the next instruction after a call (which can be
used to trap speculative execution within an infinite loop) and an
actual indirect branch to an arbitrary address.
On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this device.
For 32-bit ABIs there isn't a guaranteed scratch register and so several
different retpoline variants are introduced to use a scratch register if
one is available in the calling convention and to otherwise use direct
stack push/pop sequences to pass the target address.
This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/7625886
We also support a target feature that disables emission of the retpoline
thunk by the compiler to allow for custom thunks if users want them.
These are particularly useful in environments like kernels that
routinely do hot-patching on boot and want to hot-patch their thunk to
different code sequences. They can write this custom thunk and use
`-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this
case, on x86-64 thu thunk names must be:
```
__llvm_external_retpoline_r11
```
or on 32-bit:
```
__llvm_external_retpoline_eax
__llvm_external_retpoline_ecx
__llvm_external_retpoline_edx
__llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or in
the case of the `push` suffix on the top of the stack via a `pushl`
instruction.
There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.
The only other indirect branches remaining that we are aware of are from
precompiled runtimes (such as crt0.o and similar). The ones we have
found are not really attackable, and so we have not focused on them
here, but eventually these runtimes should also be replicated for
retpoline-ed configurations for completeness.
For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z retpolineplt`
(or use similar functionality from some other linker). We strongly
recommend also using `-z now` as non-lazy binding allows the
retpoline-mitigated PLT to be substantially smaller.
When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately 2%)
even for extremely syscall-heavy applications. This is largely due to
the small number of indirect branches that occur in performance
sensitive paths of the kernel.
When using these patches on statically linked applications, especially
C++ applications, you should expect to see a much more dramatic
performance hit. For microbenchmarks that are switch, indirect-, or
virtual-call heavy we have seen overheads ranging from 10% to 50%.
However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically reduce
the impact of hot indirect calls (by speculatively promoting them to
direct calls) and allow optimized search trees to be used to lower
switches. If you need to deploy these techniques in C++ applications, we
*strongly* recommend that you ensure all hot call targets are statically
linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well
tuned servers using all of these techniques saw 5% - 10% overhead from
the use of retpoline.
We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality available
as soon as possible. Happy for more code review, but we'd really like to
get these patches landed and backported ASAP for obvious reasons. We're
planning to backport this to both 6.0 and 5.0 release streams and get
a 5.0 release with just this cherry picked ASAP for distros and vendors.
This patch is the work of a number of people over the past month: Eric, Reid,
Rui, and myself. I'm mailing it out as a single commit due to the time
sensitive nature of landing this and the need to backport it. Huge thanks to
everyone who helped out here, and everyone at Intel who helped out in
discussions about how to craft this. Also, credit goes to Paul Turner (at
Google, but not an LLVM contributor) for much of the underlying retpoline
design.
Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer
Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41723
llvm-svn: 323155
2018-01-23 06:05:25 +08:00
|
|
|
X86RetpolineThunks.cpp
|
2015-02-02 00:15:07 +08:00
|
|
|
X86SelectionDAGInfo.cpp
|
2016-01-01 06:40:45 +08:00
|
|
|
X86ShuffleDecodeConstantPool.cpp
|
2015-02-02 00:15:07 +08:00
|
|
|
X86Subtarget.cpp
|
|
|
|
|
X86TargetMachine.cpp
|
|
|
|
|
X86TargetObjectFile.cpp
|
|
|
|
|
X86TargetTransformInfo.cpp
|
|
|
|
|
X86VZeroUpper.cpp
|
2016-05-19 00:10:17 +08:00
|
|
|
X86WinAllocaExpander.cpp
|
2016-06-29 01:11:15 +08:00
|
|
|
X86WinEHState.cpp
|
2015-02-02 00:15:07 +08:00
|
|
|
)
|
|
|
|
|
|
|
|
|
|
add_llvm_target(X86CodeGen ${sources})
|
|
|
|
|
|
|
|
|
|
add_subdirectory(AsmParser)
|
|
|
|
|
add_subdirectory(Disassembler)
|
|
|
|
|
add_subdirectory(InstPrinter)
|
|
|
|
|
add_subdirectory(MCTargetDesc)
|
|
|
|
|
add_subdirectory(TargetInfo)
|
|
|
|
|
add_subdirectory(Utils)
|