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llvm-project/clang/test/CodeGen/fma-builtins-constrained.c

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Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
// REQUIRES: x86-registered-target
// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-unknown-linux-gnu -target-feature +fma -O -emit-llvm -o - | FileCheck --check-prefix=COMMON --check-prefix=COMMONIR --check-prefix=UNCONSTRAINED %s
// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-unknown-linux-gnu -target-feature +fma -ffp-exception-behavior=strict -O -emit-llvm -o - | FileCheck --check-prefix=COMMON --check-prefix=COMMONIR --check-prefix=CONSTRAINED %s
// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-unknown-linux-gnu -target-feature +fma -O -S -o - | FileCheck --check-prefix=COMMON --check-prefix=CHECK-ASM --check-prefix=CHECK-ASM-UNCONSTRAINED %s
// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-unknown-linux-gnu -target-feature +fma -O -ffp-exception-behavior=strict -S -o - | FileCheck --check-prefix=COMMON --check-prefix=CHECK-ASM --check-prefix=CHECK-ASM-CONSTRAINED %s
#include <immintrin.h>
__m128 test_mm_fmadd_ps(__m128 a, __m128 b, __m128 c) {
// COMMON-LABEL: test_mm_fmadd_ps
// UNCONSTRAINED: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
// CONSTRAINED: call <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfmadd213ps
return _mm_fmadd_ps(a, b, c);
}
__m128d test_mm_fmadd_pd(__m128d a, __m128d b, __m128d c) {
// COMMON-LABEL: test_mm_fmadd_pd
// UNCONSTRAINED: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
// CONSTRAINED: call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfmadd213pd
return _mm_fmadd_pd(a, b, c);
}
__m128 test_mm_fmadd_ss(__m128 a, __m128 b, __m128 c) {
// COMMON-LABEL: test_mm_fmadd_ss
// COMMONIR: extractelement <4 x float> %{{.*}}, i64 0
// COMMONIR: extractelement <4 x float> %{{.*}}, i64 0
// COMMONIR: extractelement <4 x float> %{{.*}}, i64 0
// UNCONSTRAINED: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
// CONSTRAINED: call float @llvm.experimental.constrained.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfmadd213ss
// COMMONIR: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
return _mm_fmadd_ss(a, b, c);
}
__m128d test_mm_fmadd_sd(__m128d a, __m128d b, __m128d c) {
// COMMON-LABEL: test_mm_fmadd_sd
// COMMONIR: extractelement <2 x double> %{{.*}}, i64 0
// COMMONIR: extractelement <2 x double> %{{.*}}, i64 0
// COMMONIR: extractelement <2 x double> %{{.*}}, i64 0
// UNCONSTRAINED: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
// CONSTRAINED: call double @llvm.experimental.constrained.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfmadd213sd
// COMMONIR: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
return _mm_fmadd_sd(a, b, c);
}
__m128 test_mm_fmsub_ps(__m128 a, __m128 b, __m128 c) {
// COMMON-LABEL: test_mm_fmsub_ps
// COMMONIR: [[NEG:%.+]] = fneg <4 x float> %{{.+}}
// UNCONSTRAINED: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
// CONSTRAINED: call <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfmsub213ps
return _mm_fmsub_ps(a, b, c);
}
__m128d test_mm_fmsub_pd(__m128d a, __m128d b, __m128d c) {
// COMMON-LABEL: test_mm_fmsub_pd
// COMMONIR: [[NEG:%.+]] = fneg <2 x double> %{{.+}}
// UNCONSTRAINED: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
// CONSTRAINED: call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfmsub213pd
return _mm_fmsub_pd(a, b, c);
}
__m128 test_mm_fmsub_ss(__m128 a, __m128 b, __m128 c) {
// COMMON-LABEL: test_mm_fmsub_ss
// COMMONIR: extractelement <4 x float> %{{.*}}, i64 0
// COMMONIR: extractelement <4 x float> %{{.*}}, i64 0
// COMMONIR: extractelement <4 x float> %{{.*}}, i64 0
[instcombine] remove fsub to fneg hacks; only emit fneg Summary: Rewrite the fsub-0.0 idiom to fneg and always emit fneg for fp negation. This also extends the scalarization cost in instcombine for unary operators to result in the same IR rewrites for fneg as for the idiom. Reviewed By: cameron.mcinally Differential Revision: https://reviews.llvm.org/D75467
2020-03-10 23:05:31 +08:00
// COMMONIR: [[NEG:%.+]] = fneg float %{{.+}}
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
// UNCONSTRAINED: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
// CONSTRAINED: call float @llvm.experimental.constrained.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfmsub213ss
// COMMONIR: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
return _mm_fmsub_ss(a, b, c);
}
__m128d test_mm_fmsub_sd(__m128d a, __m128d b, __m128d c) {
// COMMON-LABEL: test_mm_fmsub_sd
// COMMONIR: extractelement <2 x double> %{{.*}}, i64 0
// COMMONIR: extractelement <2 x double> %{{.*}}, i64 0
// COMMONIR: extractelement <2 x double> %{{.*}}, i64 0
[instcombine] remove fsub to fneg hacks; only emit fneg Summary: Rewrite the fsub-0.0 idiom to fneg and always emit fneg for fp negation. This also extends the scalarization cost in instcombine for unary operators to result in the same IR rewrites for fneg as for the idiom. Reviewed By: cameron.mcinally Differential Revision: https://reviews.llvm.org/D75467
2020-03-10 23:05:31 +08:00
// COMMONIR: [[NEG:%.+]] = fneg double %{{.+}}
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
// UNCONSTRAINED: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
// CONSTRAINED: call double @llvm.experimental.constrained.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfmsub213sd
// COMMONIR: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
return _mm_fmsub_sd(a, b, c);
}
__m128 test_mm_fnmadd_ps(__m128 a, __m128 b, __m128 c) {
// COMMON-LABEL: test_mm_fnmadd_ps
// COMMONIR: [[NEG:%.+]] = fneg <4 x float> %{{.+}}
// UNCONSTRAINED: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
// CONSTRAINED: call <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfnmadd213ps
return _mm_fnmadd_ps(a, b, c);
}
__m128d test_mm_fnmadd_pd(__m128d a, __m128d b, __m128d c) {
// COMMON-LABEL: test_mm_fnmadd_pd
// COMMONIR: [[NEG:%.+]] = fneg <2 x double> %{{.+}}
// UNCONSTRAINED: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
// CONSTRAINED: call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfnmadd213pd
return _mm_fnmadd_pd(a, b, c);
}
__m128 test_mm_fnmadd_ss(__m128 a, __m128 b, __m128 c) {
// COMMON-LABEL: test_mm_fnmadd_ss
// COMMONIR: extractelement <4 x float> %{{.*}}, i64 0
// COMMONIR: extractelement <4 x float> %{{.*}}, i64 0
[instcombine] remove fsub to fneg hacks; only emit fneg Summary: Rewrite the fsub-0.0 idiom to fneg and always emit fneg for fp negation. This also extends the scalarization cost in instcombine for unary operators to result in the same IR rewrites for fneg as for the idiom. Reviewed By: cameron.mcinally Differential Revision: https://reviews.llvm.org/D75467
2020-03-10 23:05:31 +08:00
// COMMONIR: [[NEG:%.+]] = fneg float %{{.+}}
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
// COMMONIR: extractelement <4 x float> %{{.*}}, i64 0
// UNCONSTRAINED: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
// CONSTRAINED: call float @llvm.experimental.constrained.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfnmadd213ss
// COMMONIR: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
return _mm_fnmadd_ss(a, b, c);
}
__m128d test_mm_fnmadd_sd(__m128d a, __m128d b, __m128d c) {
// COMMON-LABEL: test_mm_fnmadd_sd
// COMMONIR: extractelement <2 x double> %{{.*}}, i64 0
// COMMONIR: extractelement <2 x double> %{{.*}}, i64 0
[instcombine] remove fsub to fneg hacks; only emit fneg Summary: Rewrite the fsub-0.0 idiom to fneg and always emit fneg for fp negation. This also extends the scalarization cost in instcombine for unary operators to result in the same IR rewrites for fneg as for the idiom. Reviewed By: cameron.mcinally Differential Revision: https://reviews.llvm.org/D75467
2020-03-10 23:05:31 +08:00
// COMMONIR: [[NEG:%.+]] = fneg double %{{.+}}
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
// COMMONIR: extractelement <2 x double> %{{.*}}, i64 0
// UNCONSTRAINED: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
// CONSTRAINED: call double @llvm.experimental.constrained.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfnmadd213sd
// COMMONIR: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
return _mm_fnmadd_sd(a, b, c);
}
__m128 test_mm_fnmsub_ps(__m128 a, __m128 b, __m128 c) {
// COMMON-LABEL: test_mm_fnmsub_ps
// COMMONIR: [[NEG:%.+]] = fneg <4 x float> %{{.+}}
// COMMONIR: [[NEG2:%.+]] = fneg <4 x float> %{{.+}}
// UNCONSTRAINED: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
// CONSTRAINED: call <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfnmsub213ps
return _mm_fnmsub_ps(a, b, c);
}
__m128d test_mm_fnmsub_pd(__m128d a, __m128d b, __m128d c) {
// COMMON-LABEL: test_mm_fnmsub_pd
// COMMONIR: [[NEG:%.+]] = fneg <2 x double> %{{.+}}
// COMMONIR: [[NEG2:%.+]] = fneg <2 x double> %{{.+}}
// UNCONSTRAINED: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
// CONSTRAINED: call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfnmsub213pd
return _mm_fnmsub_pd(a, b, c);
}
__m128 test_mm_fnmsub_ss(__m128 a, __m128 b, __m128 c) {
// COMMON-LABEL: test_mm_fnmsub_ss
// COMMONIR: extractelement <4 x float> %{{.*}}, i64 0
// COMMONIR: extractelement <4 x float> %{{.*}}, i64 0
[instcombine] remove fsub to fneg hacks; only emit fneg Summary: Rewrite the fsub-0.0 idiom to fneg and always emit fneg for fp negation. This also extends the scalarization cost in instcombine for unary operators to result in the same IR rewrites for fneg as for the idiom. Reviewed By: cameron.mcinally Differential Revision: https://reviews.llvm.org/D75467
2020-03-10 23:05:31 +08:00
// COMMONIR: [[NEG:%.+]] = fneg float %{{.+}}
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
// COMMONIR: extractelement <4 x float> %{{.*}}, i64 0
[instcombine] remove fsub to fneg hacks; only emit fneg Summary: Rewrite the fsub-0.0 idiom to fneg and always emit fneg for fp negation. This also extends the scalarization cost in instcombine for unary operators to result in the same IR rewrites for fneg as for the idiom. Reviewed By: cameron.mcinally Differential Revision: https://reviews.llvm.org/D75467
2020-03-10 23:05:31 +08:00
// COMMONIR: [[NEG2:%.+]] = fneg float %{{.+}}
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
// UNCONSTRAINED: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
// CONSTRAINED: call float @llvm.experimental.constrained.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfnmsub213ss
// COMMONIR: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
return _mm_fnmsub_ss(a, b, c);
}
__m128d test_mm_fnmsub_sd(__m128d a, __m128d b, __m128d c) {
// COMMON-LABEL: test_mm_fnmsub_sd
// COMMONIR: extractelement <2 x double> %{{.*}}, i64 0
// COMMONIR: extractelement <2 x double> %{{.*}}, i64 0
[instcombine] remove fsub to fneg hacks; only emit fneg Summary: Rewrite the fsub-0.0 idiom to fneg and always emit fneg for fp negation. This also extends the scalarization cost in instcombine for unary operators to result in the same IR rewrites for fneg as for the idiom. Reviewed By: cameron.mcinally Differential Revision: https://reviews.llvm.org/D75467
2020-03-10 23:05:31 +08:00
// COMMONIR: [[NEG:%.+]] = fneg double %{{.+}}
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
// COMMONIR: extractelement <2 x double> %{{.*}}, i64 0
[instcombine] remove fsub to fneg hacks; only emit fneg Summary: Rewrite the fsub-0.0 idiom to fneg and always emit fneg for fp negation. This also extends the scalarization cost in instcombine for unary operators to result in the same IR rewrites for fneg as for the idiom. Reviewed By: cameron.mcinally Differential Revision: https://reviews.llvm.org/D75467
2020-03-10 23:05:31 +08:00
// COMMONIR: [[NEG2:%.+]] = fneg double %{{.+}}
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
// UNCONSTRAINED: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
// CONSTRAINED: call double @llvm.experimental.constrained.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfnmsub213sd
// COMMONIR: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
return _mm_fnmsub_sd(a, b, c);
}
__m128 test_mm_fmaddsub_ps(__m128 a, __m128 b, __m128 c) {
// COMMON-LABEL: test_mm_fmaddsub_ps
[X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation Previously we emitted an fmadd and a fmadd+fneg and combined them with a shufflevector. But this doesn't follow the correct exception behavior for unselected elements so the backend can't merge them into the fmaddsub/fmsubadd instructions. This patch restores the the fmaddsub intrinsics so we don't have two arithmetic operations. We lose out on optimization opportunity in the non-strict FP case, but I don't think this is a big loss. If someone gives us a test case we can look into adding instcombine/dagcombine improvements. I'd rather not have the frontend do completely different things for strict and non-strict. This still has problems because target specific intrinsics don't support strict semantics yet. We also still have all of the problems with masking. But we at least generate the right instruction in constrained mode now. Differential Revision: https://reviews.llvm.org/D74268
2020-02-25 04:06:55 +08:00
// COMMONIR-NOT: fneg
// COMMONIR: tail call <4 x float> @llvm.x86.fma.vfmaddsub.ps(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
// CHECK-ASM: vfmaddsub213ps
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
return _mm_fmaddsub_ps(a, b, c);
}
__m128d test_mm_fmaddsub_pd(__m128d a, __m128d b, __m128d c) {
// COMMON-LABEL: test_mm_fmaddsub_pd
[X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation Previously we emitted an fmadd and a fmadd+fneg and combined them with a shufflevector. But this doesn't follow the correct exception behavior for unselected elements so the backend can't merge them into the fmaddsub/fmsubadd instructions. This patch restores the the fmaddsub intrinsics so we don't have two arithmetic operations. We lose out on optimization opportunity in the non-strict FP case, but I don't think this is a big loss. If someone gives us a test case we can look into adding instcombine/dagcombine improvements. I'd rather not have the frontend do completely different things for strict and non-strict. This still has problems because target specific intrinsics don't support strict semantics yet. We also still have all of the problems with masking. But we at least generate the right instruction in constrained mode now. Differential Revision: https://reviews.llvm.org/D74268
2020-02-25 04:06:55 +08:00
// COMMONIR-NOT: fneg
// COMMONIR: tail call <2 x double> @llvm.x86.fma.vfmaddsub.pd(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
// CHECK-ASM: vfmaddsub213pd
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
return _mm_fmaddsub_pd(a, b, c);
}
__m128 test_mm_fmsubadd_ps(__m128 a, __m128 b, __m128 c) {
// COMMON-LABEL: test_mm_fmsubadd_ps
[X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation Previously we emitted an fmadd and a fmadd+fneg and combined them with a shufflevector. But this doesn't follow the correct exception behavior for unselected elements so the backend can't merge them into the fmaddsub/fmsubadd instructions. This patch restores the the fmaddsub intrinsics so we don't have two arithmetic operations. We lose out on optimization opportunity in the non-strict FP case, but I don't think this is a big loss. If someone gives us a test case we can look into adding instcombine/dagcombine improvements. I'd rather not have the frontend do completely different things for strict and non-strict. This still has problems because target specific intrinsics don't support strict semantics yet. We also still have all of the problems with masking. But we at least generate the right instruction in constrained mode now. Differential Revision: https://reviews.llvm.org/D74268
2020-02-25 04:06:55 +08:00
// COMMONIR: [[FNEG:%.+]] = fneg <4 x float> %{{.*}}
// COMMONIR: tail call <4 x float> @llvm.x86.fma.vfmaddsub.ps(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[FNEG]])
// CHECK-ASM: vfmsubadd213ps
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
return _mm_fmsubadd_ps(a, b, c);
}
__m128d test_mm_fmsubadd_pd(__m128d a, __m128d b, __m128d c) {
// COMMON-LABEL: test_mm_fmsubadd_pd
[X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation Previously we emitted an fmadd and a fmadd+fneg and combined them with a shufflevector. But this doesn't follow the correct exception behavior for unselected elements so the backend can't merge them into the fmaddsub/fmsubadd instructions. This patch restores the the fmaddsub intrinsics so we don't have two arithmetic operations. We lose out on optimization opportunity in the non-strict FP case, but I don't think this is a big loss. If someone gives us a test case we can look into adding instcombine/dagcombine improvements. I'd rather not have the frontend do completely different things for strict and non-strict. This still has problems because target specific intrinsics don't support strict semantics yet. We also still have all of the problems with masking. But we at least generate the right instruction in constrained mode now. Differential Revision: https://reviews.llvm.org/D74268
2020-02-25 04:06:55 +08:00
// COMMONIR: [[FNEG:%.+]] = fneg <2 x double> %{{.*}}
// COMMONIR: tail call <2 x double> @llvm.x86.fma.vfmaddsub.pd(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[FNEG]])
// CHECK-ASM: vfmsubadd213pd
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
return _mm_fmsubadd_pd(a, b, c);
}
__m256 test_mm256_fmadd_ps(__m256 a, __m256 b, __m256 c) {
// COMMON-LABEL: test_mm256_fmadd_ps
// UNCONSTRAINED: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}})
// CONSTRAINED: call <8 x float> @llvm.experimental.constrained.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfmadd213ps
return _mm256_fmadd_ps(a, b, c);
}
__m256d test_mm256_fmadd_pd(__m256d a, __m256d b, __m256d c) {
// COMMON-LABEL: test_mm256_fmadd_pd
// UNCONSTRAINED: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}})
// CONSTRAINED: call <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfmadd213pd
return _mm256_fmadd_pd(a, b, c);
}
__m256 test_mm256_fmsub_ps(__m256 a, __m256 b, __m256 c) {
// COMMON-LABEL: test_mm256_fmsub_ps
// COMMONIR: [[NEG:%.+]] = fneg <8 x float> %{{.*}}
// UNCONSTRAINED: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}})
// CONSTRAINED: call <8 x float> @llvm.experimental.constrained.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfmsub213ps
return _mm256_fmsub_ps(a, b, c);
}
__m256d test_mm256_fmsub_pd(__m256d a, __m256d b, __m256d c) {
// COMMON-LABEL: test_mm256_fmsub_pd
// COMMONIR: [[NEG:%.+]] = fneg <4 x double> %{{.+}}
// UNCONSTRAINED: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}})
// CONSTRAINED: call <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfmsub213pd
return _mm256_fmsub_pd(a, b, c);
}
__m256 test_mm256_fnmadd_ps(__m256 a, __m256 b, __m256 c) {
// COMMON-LABEL: test_mm256_fnmadd_ps
// COMMONIR: [[NEG:%.+]] = fneg <8 x float> %{{.*}}
// UNCONSTRAINED: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}})
// CONSTRAINED: call <8 x float> @llvm.experimental.constrained.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfnmadd213ps
return _mm256_fnmadd_ps(a, b, c);
}
__m256d test_mm256_fnmadd_pd(__m256d a, __m256d b, __m256d c) {
// COMMON-LABEL: test_mm256_fnmadd_pd
// COMMONIR: [[NEG:%.+]] = fneg <4 x double> %{{.+}}
// UNCONSTRAINED: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}})
// CONSTRAINED: call <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfnmadd213pd
return _mm256_fnmadd_pd(a, b, c);
}
__m256 test_mm256_fnmsub_ps(__m256 a, __m256 b, __m256 c) {
// COMMON-LABEL: test_mm256_fnmsub_ps
// COMMONIR: [[NEG:%.+]] = fneg <8 x float> %{{.*}}
// COMMONIR: [[NEG2:%.+]] = fneg <8 x float> %{{.*}}
// UNCONSTRAINED: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}})
// CONSTRAINED: call <8 x float> @llvm.experimental.constrained.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfnmsub213ps
return _mm256_fnmsub_ps(a, b, c);
}
__m256d test_mm256_fnmsub_pd(__m256d a, __m256d b, __m256d c) {
// COMMON-LABEL: test_mm256_fnmsub_pd
// COMMONIR: [[NEG:%.+]] = fneg <4 x double> %{{.+}}
// COMMONIR: [[NEG2:%.+]] = fneg <4 x double> %{{.+}}
// UNCONSTRAINED: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}})
// CONSTRAINED: call <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !{{.*}})
// CHECK-ASM: vfnmsub213pd
return _mm256_fnmsub_pd(a, b, c);
}
__m256 test_mm256_fmaddsub_ps(__m256 a, __m256 b, __m256 c) {
// COMMON-LABEL: test_mm256_fmaddsub_ps
[X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation Previously we emitted an fmadd and a fmadd+fneg and combined them with a shufflevector. But this doesn't follow the correct exception behavior for unselected elements so the backend can't merge them into the fmaddsub/fmsubadd instructions. This patch restores the the fmaddsub intrinsics so we don't have two arithmetic operations. We lose out on optimization opportunity in the non-strict FP case, but I don't think this is a big loss. If someone gives us a test case we can look into adding instcombine/dagcombine improvements. I'd rather not have the frontend do completely different things for strict and non-strict. This still has problems because target specific intrinsics don't support strict semantics yet. We also still have all of the problems with masking. But we at least generate the right instruction in constrained mode now. Differential Revision: https://reviews.llvm.org/D74268
2020-02-25 04:06:55 +08:00
// COMMONIR-NOT: fneg
// COMMONIR: tail call <8 x float> @llvm.x86.fma.vfmaddsub.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}})
// CHECK-ASM: vfmaddsub213ps
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
return _mm256_fmaddsub_ps(a, b, c);
}
__m256d test_mm256_fmaddsub_pd(__m256d a, __m256d b, __m256d c) {
// COMMON-LABEL: test_mm256_fmaddsub_pd
[X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation Previously we emitted an fmadd and a fmadd+fneg and combined them with a shufflevector. But this doesn't follow the correct exception behavior for unselected elements so the backend can't merge them into the fmaddsub/fmsubadd instructions. This patch restores the the fmaddsub intrinsics so we don't have two arithmetic operations. We lose out on optimization opportunity in the non-strict FP case, but I don't think this is a big loss. If someone gives us a test case we can look into adding instcombine/dagcombine improvements. I'd rather not have the frontend do completely different things for strict and non-strict. This still has problems because target specific intrinsics don't support strict semantics yet. We also still have all of the problems with masking. But we at least generate the right instruction in constrained mode now. Differential Revision: https://reviews.llvm.org/D74268
2020-02-25 04:06:55 +08:00
// COMMONIR-NOT: fneg
// COMMONIR: tail call <4 x double> @llvm.x86.fma.vfmaddsub.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}})
// CHECK-ASM: vfmaddsub213pd
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
return _mm256_fmaddsub_pd(a, b, c);
}
__m256 test_mm256_fmsubadd_ps(__m256 a, __m256 b, __m256 c) {
// COMMON-LABEL: test_mm256_fmsubadd_ps
[X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation Previously we emitted an fmadd and a fmadd+fneg and combined them with a shufflevector. But this doesn't follow the correct exception behavior for unselected elements so the backend can't merge them into the fmaddsub/fmsubadd instructions. This patch restores the the fmaddsub intrinsics so we don't have two arithmetic operations. We lose out on optimization opportunity in the non-strict FP case, but I don't think this is a big loss. If someone gives us a test case we can look into adding instcombine/dagcombine improvements. I'd rather not have the frontend do completely different things for strict and non-strict. This still has problems because target specific intrinsics don't support strict semantics yet. We also still have all of the problems with masking. But we at least generate the right instruction in constrained mode now. Differential Revision: https://reviews.llvm.org/D74268
2020-02-25 04:06:55 +08:00
// COMMONIR: [[FNEG:%.+]] = fneg <8 x float> %{{.*}}
// COMMONIR: tail call <8 x float> @llvm.x86.fma.vfmaddsub.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[FNEG]])
// CHECK-ASM: vfmsubadd213ps
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
return _mm256_fmsubadd_ps(a, b, c);
}
__m256d test_mm256_fmsubadd_pd(__m256d a, __m256d b, __m256d c) {
// COMMON-LABEL: test_mm256_fmsubadd_pd
[X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation Previously we emitted an fmadd and a fmadd+fneg and combined them with a shufflevector. But this doesn't follow the correct exception behavior for unselected elements so the backend can't merge them into the fmaddsub/fmsubadd instructions. This patch restores the the fmaddsub intrinsics so we don't have two arithmetic operations. We lose out on optimization opportunity in the non-strict FP case, but I don't think this is a big loss. If someone gives us a test case we can look into adding instcombine/dagcombine improvements. I'd rather not have the frontend do completely different things for strict and non-strict. This still has problems because target specific intrinsics don't support strict semantics yet. We also still have all of the problems with masking. But we at least generate the right instruction in constrained mode now. Differential Revision: https://reviews.llvm.org/D74268
2020-02-25 04:06:55 +08:00
// COMMONIR: [[FNEG:%.+]] = fneg <4 x double> %{{.*}}
// COMMONIR: tail call <4 x double> @llvm.x86.fma.vfmaddsub.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> [[FNEG]])
// CHECK-ASM: vfmsubadd213pd
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement" With REQUIRES: x86-register-target added to the tests. Also remove some unneeded FIXMEs But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with constrained FP. Original patch by Kevin P. Neal
2020-02-07 08:23:54 +08:00
return _mm256_fmsubadd_pd(a, b, c);
}