2019-02-05 01:18:11 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefix=X86
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declare i4 @llvm.umul.fix.i4 (i4, i4, i32)
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declare i32 @llvm.umul.fix.i32 (i32, i32, i32)
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declare i64 @llvm.umul.fix.i64 (i64, i64, i32)
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declare <4 x i32> @llvm.umul.fix.v4i32(<4 x i32>, <4 x i32>, i32)
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define i32 @func(i32 %x, i32 %y) nounwind {
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; X64-LABEL: func:
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; X64: # %bb.0:
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; X64-NEXT: movl %esi, %eax
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; X64-NEXT: movl %edi, %ecx
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; X64-NEXT: imulq %rax, %rcx
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; X64-NEXT: movq %rcx, %rax
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; X64-NEXT: shrq $32, %rax
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; X64-NEXT: shldl $30, %ecx, %eax
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; X64-NEXT: # kill: def $eax killed $eax killed $rax
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; X64-NEXT: retq
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;
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; X86-LABEL: func:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: mull {{[0-9]+}}(%esp)
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; X86-NEXT: shrdl $2, %edx, %eax
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; X86-NEXT: retl
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2019-08-12 03:27:14 +08:00
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%tmp = call i32 @llvm.umul.fix.i32(i32 %x, i32 %y, i32 2)
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ret i32 %tmp
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2019-02-05 01:18:11 +08:00
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}
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; X64-LABEL: func2:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: mulq %rsi
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; X64-NEXT: shrdq $2, %rdx, %rax
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; X64-NEXT: retq
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;
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; X86-LABEL: func2:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebp
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: mull {{[0-9]+}}(%esp)
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; X86-NEXT: movl %edx, %edi
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; X86-NEXT: movl %eax, %ebx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: mull {{[0-9]+}}(%esp)
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: movl %edx, %ebp
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; X86-NEXT: addl %ebx, %ebp
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; X86-NEXT: adcl $0, %edi
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; X86-NEXT: movl %esi, %eax
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; X86-NEXT: mull {{[0-9]+}}(%esp)
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; X86-NEXT: addl %ebp, %eax
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; X86-NEXT: adcl %edi, %edx
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; X86-NEXT: imull {{[0-9]+}}(%esp), %esi
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[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX
Summary:
Simplify the right shift of the intermediate result (given
in four parts) by using funnel shift.
There are some impact on lit tests, but that seems to be
related to register allocation differences due to how FSHR
is expanded on X86 (giving a slightly different operand order
for the OR operations compared to the old code).
Reviewers: leonardchan, RKSimon, spatel, lebedev.ri
Reviewed By: RKSimon
Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, s.egerton, pzheng, bevinh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67036
llvm-svn: 370813
2019-09-04 03:35:07 +08:00
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; X86-NEXT: addl %edx, %esi
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; X86-NEXT: shldl $30, %eax, %esi
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2019-02-05 01:18:11 +08:00
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; X86-NEXT: shldl $30, %ecx, %eax
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[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX
Summary:
Simplify the right shift of the intermediate result (given
in four parts) by using funnel shift.
There are some impact on lit tests, but that seems to be
related to register allocation differences due to how FSHR
is expanded on X86 (giving a slightly different operand order
for the OR operations compared to the old code).
Reviewers: leonardchan, RKSimon, spatel, lebedev.ri
Reviewed By: RKSimon
Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, s.egerton, pzheng, bevinh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67036
llvm-svn: 370813
2019-09-04 03:35:07 +08:00
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; X86-NEXT: movl %esi, %edx
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2019-02-05 01:18:11 +08:00
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: popl %ebx
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl
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2019-08-12 03:27:14 +08:00
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%tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 2)
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ret i64 %tmp
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2019-02-05 01:18:11 +08:00
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}
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define i4 @func3(i4 %x, i4 %y) nounwind {
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; X64-LABEL: func3:
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; X64: # %bb.0:
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2019-03-28 03:54:41 +08:00
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: andl $15, %esi
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; X64-NEXT: andl $15, %eax
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; X64-NEXT: imull %esi, %eax
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2019-02-05 01:18:11 +08:00
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; X64-NEXT: shrb $2, %al
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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;
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; X86-LABEL: func3:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: andb $15, %al
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; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X86-NEXT: andb $15, %cl
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; X86-NEXT: movzbl %cl, %ecx
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; X86-NEXT: movzbl %al, %eax
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; X86-NEXT: imull %ecx, %eax
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; X86-NEXT: shrb $2, %al
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; X86-NEXT: # kill: def $al killed $al killed $eax
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; X86-NEXT: retl
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2019-08-12 03:27:14 +08:00
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%tmp = call i4 @llvm.umul.fix.i4(i4 %x, i4 %y, i32 2)
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ret i4 %tmp
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2019-02-05 01:18:11 +08:00
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}
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define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
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; X64-LABEL: vec:
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; X64: # %bb.0:
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; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; X64-NEXT: pmuludq %xmm1, %xmm0
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2019-02-09 02:57:38 +08:00
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; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,2,2,3]
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2019-02-05 01:18:11 +08:00
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; X64-NEXT: pmuludq %xmm2, %xmm1
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2019-02-09 02:57:38 +08:00
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; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,2,2,3]
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2019-02-05 01:18:11 +08:00
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; X64-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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2019-02-09 02:57:38 +08:00
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; X64-NEXT: psrld $2, %xmm3
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; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
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2019-02-05 01:18:11 +08:00
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; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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2019-02-09 02:57:38 +08:00
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; X64-NEXT: pslld $30, %xmm0
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2019-02-05 01:18:11 +08:00
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; X64-NEXT: por %xmm3, %xmm0
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; X64-NEXT: retq
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;
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; X86-LABEL: vec:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebp
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: mull {{[0-9]+}}(%esp)
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; X86-NEXT: movl %edx, %ebp
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; X86-NEXT: shldl $30, %eax, %ebp
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; X86-NEXT: movl %ebx, %eax
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; X86-NEXT: mull {{[0-9]+}}(%esp)
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; X86-NEXT: movl %edx, %ebx
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; X86-NEXT: shldl $30, %eax, %ebx
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; X86-NEXT: movl %edi, %eax
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; X86-NEXT: mull {{[0-9]+}}(%esp)
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; X86-NEXT: movl %edx, %edi
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; X86-NEXT: shldl $30, %eax, %edi
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; X86-NEXT: movl %esi, %eax
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; X86-NEXT: mull {{[0-9]+}}(%esp)
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; X86-NEXT: shldl $30, %eax, %edx
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; X86-NEXT: movl %edx, 12(%ecx)
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; X86-NEXT: movl %edi, 8(%ecx)
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; X86-NEXT: movl %ebx, 4(%ecx)
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; X86-NEXT: movl %ebp, (%ecx)
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: popl %ebx
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl $4
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2019-08-12 03:27:14 +08:00
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%tmp = call <4 x i32> @llvm.umul.fix.v4i32(<4 x i32> %x, <4 x i32> %y, i32 2)
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ret <4 x i32> %tmp
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2019-02-05 01:18:11 +08:00
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}
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; These result in regular integer multiplication
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define i32 @func4(i32 %x, i32 %y) nounwind {
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; X64-LABEL: func4:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: imull %esi, %eax
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; X64-NEXT: retq
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;
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; X86-LABEL: func4:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: imull {{[0-9]+}}(%esp), %eax
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; X86-NEXT: retl
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2019-08-12 03:27:14 +08:00
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%tmp = call i32 @llvm.umul.fix.i32(i32 %x, i32 %y, i32 0)
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ret i32 %tmp
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2019-02-05 01:18:11 +08:00
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}
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define i64 @func5(i64 %x, i64 %y) nounwind {
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; X64-LABEL: func5:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: imulq %rsi, %rax
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; X64-NEXT: retq
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;
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; X86-LABEL: func5:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: mull %esi
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; X86-NEXT: imull {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: addl %ecx, %edx
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; X86-NEXT: imull {{[0-9]+}}(%esp), %esi
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; X86-NEXT: addl %esi, %edx
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; X86-NEXT: popl %esi
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|
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; X86-NEXT: retl
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2019-08-12 03:27:14 +08:00
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|
|
%tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 0)
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|
ret i64 %tmp
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2019-02-05 01:18:11 +08:00
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|
|
}
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define i4 @func6(i4 %x, i4 %y) nounwind {
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|
|
; X64-LABEL: func6:
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|
|
|
; X64: # %bb.0:
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|
|
; X64-NEXT: movl %edi, %eax
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; X64-NEXT: andb $15, %al
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; X64-NEXT: andb $15, %sil
|
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|
|
; X64-NEXT: # kill: def $al killed $al killed $eax
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|
|
|
; X64-NEXT: mulb %sil
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; X64-NEXT: retq
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;
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|
|
|
; X86-LABEL: func6:
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|
|
|
; X86: # %bb.0:
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|
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
|
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|
|
; X86-NEXT: andb $15, %al
|
|
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
|
|
|
|
; X86-NEXT: andb $15, %cl
|
|
|
|
; X86-NEXT: mulb %cl
|
|
|
|
; X86-NEXT: retl
|
2019-08-12 03:27:14 +08:00
|
|
|
%tmp = call i4 @llvm.umul.fix.i4(i4 %x, i4 %y, i32 0)
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|
|
|
ret i4 %tmp
|
2019-02-05 01:18:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @vec2(<4 x i32> %x, <4 x i32> %y) nounwind {
|
|
|
|
; X64-LABEL: vec2:
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|
|
|
; X64: # %bb.0:
|
|
|
|
; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
|
|
|
|
; X64-NEXT: pmuludq %xmm1, %xmm0
|
|
|
|
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
|
|
|
; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
|
|
|
; X64-NEXT: pmuludq %xmm2, %xmm1
|
|
|
|
; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
|
|
|
|
; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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|
|
|
; X64-NEXT: retq
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|
|
;
|
|
|
|
; X86-LABEL: vec2:
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|
|
|
; X86: # %bb.0:
|
|
|
|
; X86-NEXT: pushl %edi
|
|
|
|
; X86-NEXT: pushl %esi
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
|
|
|
|
; X86-NEXT: imull {{[0-9]+}}(%esp), %edi
|
|
|
|
; X86-NEXT: imull {{[0-9]+}}(%esp), %esi
|
|
|
|
; X86-NEXT: imull {{[0-9]+}}(%esp), %edx
|
|
|
|
; X86-NEXT: imull {{[0-9]+}}(%esp), %ecx
|
|
|
|
; X86-NEXT: movl %ecx, 12(%eax)
|
|
|
|
; X86-NEXT: movl %edx, 8(%eax)
|
|
|
|
; X86-NEXT: movl %esi, 4(%eax)
|
|
|
|
; X86-NEXT: movl %edi, (%eax)
|
|
|
|
; X86-NEXT: popl %esi
|
|
|
|
; X86-NEXT: popl %edi
|
|
|
|
; X86-NEXT: retl $4
|
2019-08-12 03:27:14 +08:00
|
|
|
%tmp = call <4 x i32> @llvm.umul.fix.v4i32(<4 x i32> %x, <4 x i32> %y, i32 0)
|
|
|
|
ret <4 x i32> %tmp
|
2019-02-05 01:18:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @func7(i64 %x, i64 %y) nounwind {
|
|
|
|
; X64-LABEL: func7:
|
|
|
|
; X64: # %bb.0:
|
|
|
|
; X64-NEXT: movq %rdi, %rax
|
|
|
|
; X64-NEXT: mulq %rsi
|
|
|
|
; X64-NEXT: shrdq $32, %rdx, %rax
|
|
|
|
; X64-NEXT: retq
|
|
|
|
;
|
|
|
|
; X86-LABEL: func7:
|
|
|
|
; X86: # %bb.0:
|
|
|
|
; X86-NEXT: pushl %ebp
|
|
|
|
; X86-NEXT: pushl %ebx
|
|
|
|
; X86-NEXT: pushl %edi
|
|
|
|
; X86-NEXT: pushl %esi
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
|
|
|
|
; X86-NEXT: movl %ecx, %eax
|
|
|
|
; X86-NEXT: mull {{[0-9]+}}(%esp)
|
|
|
|
; X86-NEXT: movl %edx, %edi
|
|
|
|
; X86-NEXT: movl %eax, %ebx
|
|
|
|
; X86-NEXT: movl %ecx, %eax
|
|
|
|
; X86-NEXT: mull %ebp
|
|
|
|
; X86-NEXT: addl %edx, %ebx
|
|
|
|
; X86-NEXT: adcl $0, %edi
|
|
|
|
; X86-NEXT: movl %esi, %eax
|
|
|
|
; X86-NEXT: mull %ebp
|
|
|
|
; X86-NEXT: addl %ebx, %eax
|
|
|
|
; X86-NEXT: adcl %edi, %edx
|
|
|
|
; X86-NEXT: imull {{[0-9]+}}(%esp), %esi
|
|
|
|
; X86-NEXT: addl %esi, %edx
|
|
|
|
; X86-NEXT: popl %esi
|
|
|
|
; X86-NEXT: popl %edi
|
|
|
|
; X86-NEXT: popl %ebx
|
|
|
|
; X86-NEXT: popl %ebp
|
|
|
|
; X86-NEXT: retl
|
2019-08-12 03:27:14 +08:00
|
|
|
%tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 32)
|
|
|
|
ret i64 %tmp
|
2019-02-05 01:18:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @func8(i64 %x, i64 %y) nounwind {
|
|
|
|
; X64-LABEL: func8:
|
|
|
|
; X64: # %bb.0:
|
|
|
|
; X64-NEXT: movq %rdi, %rax
|
|
|
|
; X64-NEXT: mulq %rsi
|
|
|
|
; X64-NEXT: shrdq $63, %rdx, %rax
|
|
|
|
; X64-NEXT: retq
|
|
|
|
;
|
|
|
|
; X86-LABEL: func8:
|
|
|
|
; X86: # %bb.0:
|
|
|
|
; X86-NEXT: pushl %ebp
|
|
|
|
; X86-NEXT: pushl %ebx
|
|
|
|
; X86-NEXT: pushl %edi
|
|
|
|
; X86-NEXT: pushl %esi
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
|
|
|
|
; X86-NEXT: movl %ecx, %eax
|
|
|
|
; X86-NEXT: mull %ebp
|
|
|
|
; X86-NEXT: movl %edx, %edi
|
|
|
|
; X86-NEXT: movl %eax, %ebx
|
|
|
|
; X86-NEXT: movl %ecx, %eax
|
|
|
|
; X86-NEXT: mull %esi
|
[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX
Summary:
Simplify the right shift of the intermediate result (given
in four parts) by using funnel shift.
There are some impact on lit tests, but that seems to be
related to register allocation differences due to how FSHR
is expanded on X86 (giving a slightly different operand order
for the OR operations compared to the old code).
Reviewers: leonardchan, RKSimon, spatel, lebedev.ri
Reviewed By: RKSimon
Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, s.egerton, pzheng, bevinh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67036
llvm-svn: 370813
2019-09-04 03:35:07 +08:00
|
|
|
; X86-NEXT: addl %edx, %ebx
|
2019-02-05 01:18:11 +08:00
|
|
|
; X86-NEXT: adcl $0, %edi
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-NEXT: mull %ebp
|
[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX
Summary:
Simplify the right shift of the intermediate result (given
in four parts) by using funnel shift.
There are some impact on lit tests, but that seems to be
related to register allocation differences due to how FSHR
is expanded on X86 (giving a slightly different operand order
for the OR operations compared to the old code).
Reviewers: leonardchan, RKSimon, spatel, lebedev.ri
Reviewed By: RKSimon
Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, s.egerton, pzheng, bevinh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67036
llvm-svn: 370813
2019-09-04 03:35:07 +08:00
|
|
|
; X86-NEXT: movl %edx, %ecx
|
2019-02-05 01:18:11 +08:00
|
|
|
; X86-NEXT: movl %eax, %ebp
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-NEXT: mull %esi
|
[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX
Summary:
Simplify the right shift of the intermediate result (given
in four parts) by using funnel shift.
There are some impact on lit tests, but that seems to be
related to register allocation differences due to how FSHR
is expanded on X86 (giving a slightly different operand order
for the OR operations compared to the old code).
Reviewers: leonardchan, RKSimon, spatel, lebedev.ri
Reviewed By: RKSimon
Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, s.egerton, pzheng, bevinh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67036
llvm-svn: 370813
2019-09-04 03:35:07 +08:00
|
|
|
; X86-NEXT: addl %ebx, %eax
|
2019-02-05 01:18:11 +08:00
|
|
|
; X86-NEXT: adcl %edi, %edx
|
[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX
Summary:
Simplify the right shift of the intermediate result (given
in four parts) by using funnel shift.
There are some impact on lit tests, but that seems to be
related to register allocation differences due to how FSHR
is expanded on X86 (giving a slightly different operand order
for the OR operations compared to the old code).
Reviewers: leonardchan, RKSimon, spatel, lebedev.ri
Reviewed By: RKSimon
Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, s.egerton, pzheng, bevinh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67036
llvm-svn: 370813
2019-09-04 03:35:07 +08:00
|
|
|
; X86-NEXT: adcl $0, %ecx
|
2019-02-05 01:18:11 +08:00
|
|
|
; X86-NEXT: addl %ebp, %edx
|
[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX
Summary:
Simplify the right shift of the intermediate result (given
in four parts) by using funnel shift.
There are some impact on lit tests, but that seems to be
related to register allocation differences due to how FSHR
is expanded on X86 (giving a slightly different operand order
for the OR operations compared to the old code).
Reviewers: leonardchan, RKSimon, spatel, lebedev.ri
Reviewed By: RKSimon
Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, s.egerton, pzheng, bevinh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67036
llvm-svn: 370813
2019-09-04 03:35:07 +08:00
|
|
|
; X86-NEXT: adcl $0, %ecx
|
|
|
|
; X86-NEXT: shldl $1, %edx, %ecx
|
2019-02-05 01:18:11 +08:00
|
|
|
; X86-NEXT: shrdl $31, %edx, %eax
|
[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX
Summary:
Simplify the right shift of the intermediate result (given
in four parts) by using funnel shift.
There are some impact on lit tests, but that seems to be
related to register allocation differences due to how FSHR
is expanded on X86 (giving a slightly different operand order
for the OR operations compared to the old code).
Reviewers: leonardchan, RKSimon, spatel, lebedev.ri
Reviewed By: RKSimon
Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, s.egerton, pzheng, bevinh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67036
llvm-svn: 370813
2019-09-04 03:35:07 +08:00
|
|
|
; X86-NEXT: movl %ecx, %edx
|
2019-02-05 01:18:11 +08:00
|
|
|
; X86-NEXT: popl %esi
|
|
|
|
; X86-NEXT: popl %edi
|
|
|
|
; X86-NEXT: popl %ebx
|
|
|
|
; X86-NEXT: popl %ebp
|
|
|
|
; X86-NEXT: retl
|
2019-08-12 03:27:14 +08:00
|
|
|
%tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 63)
|
|
|
|
ret i64 %tmp
|
2019-02-05 01:18:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @func9(i64 %x, i64 %y) nounwind {
|
|
|
|
; X64-LABEL: func9:
|
|
|
|
; X64: # %bb.0:
|
|
|
|
; X64-NEXT: movq %rdi, %rax
|
|
|
|
; X64-NEXT: mulq %rsi
|
|
|
|
; X64-NEXT: movq %rdx, %rax
|
|
|
|
; X64-NEXT: retq
|
|
|
|
;
|
|
|
|
; X86-LABEL: func9:
|
|
|
|
; X86: # %bb.0:
|
|
|
|
; X86-NEXT: pushl %ebp
|
|
|
|
; X86-NEXT: pushl %ebx
|
|
|
|
; X86-NEXT: pushl %edi
|
|
|
|
; X86-NEXT: pushl %esi
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
|
|
|
|
; X86-NEXT: movl %ecx, %eax
|
|
|
|
; X86-NEXT: mull %ebp
|
|
|
|
; X86-NEXT: movl %edx, %edi
|
|
|
|
; X86-NEXT: movl %eax, %ebx
|
|
|
|
; X86-NEXT: movl %ecx, %eax
|
|
|
|
; X86-NEXT: mull %esi
|
|
|
|
; X86-NEXT: movl %edx, %ecx
|
|
|
|
; X86-NEXT: addl %ebx, %ecx
|
|
|
|
; X86-NEXT: adcl $0, %edi
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-NEXT: mull %ebp
|
|
|
|
; X86-NEXT: movl %edx, %ebx
|
|
|
|
; X86-NEXT: movl %eax, %ebp
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-NEXT: mull %esi
|
|
|
|
; X86-NEXT: addl %ecx, %eax
|
|
|
|
; X86-NEXT: adcl %edi, %edx
|
|
|
|
; X86-NEXT: adcl $0, %ebx
|
|
|
|
; X86-NEXT: addl %edx, %ebp
|
|
|
|
; X86-NEXT: adcl $0, %ebx
|
|
|
|
; X86-NEXT: movl %ebp, %eax
|
|
|
|
; X86-NEXT: movl %ebx, %edx
|
|
|
|
; X86-NEXT: popl %esi
|
|
|
|
; X86-NEXT: popl %edi
|
|
|
|
; X86-NEXT: popl %ebx
|
|
|
|
; X86-NEXT: popl %ebp
|
|
|
|
; X86-NEXT: retl
|
2019-08-12 03:27:14 +08:00
|
|
|
%tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 64)
|
|
|
|
ret i64 %tmp
|
2019-02-05 01:18:11 +08:00
|
|
|
}
|