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llvm-project/llvm/test/CodeGen/X86/shift-bmi2.ll

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[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
; RUN: llc -mtriple=i386-unknown-unknown -mcpu=core-avx2 < %s | FileCheck --check-prefix=BMI2 %s
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 < %s | FileCheck --check-prefix=BMI264 %s
define i32 @shl32(i32 %x, i32 %shamt) nounwind uwtable readnone {
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-LABEL: shl32:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI2: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; BMI2-NEXT: shlxl %eax, {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: retl
;
; BMI264-LABEL: shl32:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: shlxl %esi, %edi, %eax
; BMI264-NEXT: retq
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = shl i32 %x, %shamt
ret i32 %shl
}
define i32 @shl32i(i32 %x) nounwind uwtable readnone {
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-LABEL: shl32i:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI2: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: shll $5, %eax
; BMI2-NEXT: retl
;
; BMI264-LABEL: shl32i:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: movl %edi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI264-NEXT: shll $5, %eax
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: retq
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = shl i32 %x, 5
ret i32 %shl
}
define i32 @shl32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-LABEL: shl32p:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI2: # %bb.0:
[X86] Add patterns for memory forms of SARX/SHLX/SHRX with careful complexity adjustment to keep shift by immediate using the legacy instructions. These patterns were only missing to favor using the legacy instructions when the shift was a constant. With careful adjustment of the pattern complexity we can make sure the immediate instructions still have priority over these patterns. llvm-svn: 308834
2017-07-23 11:59:37 +08:00
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; BMI2-NEXT: shlxl %ecx, (%eax), %eax
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-NEXT: retl
;
; BMI264-LABEL: shl32p:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: shlxl %esi, (%rdi), %eax
; BMI264-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i32, i32* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = shl i32 %x, %shamt
ret i32 %shl
}
define i32 @shl32pi(i32* %p) nounwind uwtable readnone {
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-LABEL: shl32pi:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI2: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: movl (%eax), %eax
; BMI2-NEXT: shll $5, %eax
; BMI2-NEXT: retl
;
; BMI264-LABEL: shl32pi:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: movl (%rdi), %eax
; BMI264-NEXT: shll $5, %eax
; BMI264-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i32, i32* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = shl i32 %x, 5
ret i32 %shl
}
define i64 @shl64(i64 %x, i64 %shamt) nounwind uwtable readnone {
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI2-LABEL: shl64:
; BMI2: # %bb.0:
; BMI2-NEXT: pushl %esi
; BMI2-NEXT: .cfi_def_cfa_offset 8
; BMI2-NEXT: .cfi_offset %esi, -8
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; BMI2-NEXT: shldl %cl, %eax, %edx
; BMI2-NEXT: shlxl %ecx, %eax, %esi
; BMI2-NEXT: xorl %eax, %eax
; BMI2-NEXT: testb $32, %cl
; BMI2-NEXT: cmovnel %esi, %edx
; BMI2-NEXT: cmovel %esi, %eax
; BMI2-NEXT: popl %esi
; BMI2-NEXT: .cfi_def_cfa_offset 4
; BMI2-NEXT: retl
;
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-LABEL: shl64:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: shlxq %rsi, %rdi, %rax
; BMI264-NEXT: retq
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = shl i64 %x, %shamt
ret i64 %shl
}
define i64 @shl64i(i64 %x) nounwind uwtable readnone {
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI2-LABEL: shl64i:
; BMI2: # %bb.0:
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; BMI2-NEXT: shldl $7, %eax, %edx
; BMI2-NEXT: shll $7, %eax
; BMI2-NEXT: retl
;
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-LABEL: shl64i:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: movq %rdi, %rax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI264-NEXT: shlq $7, %rax
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: retq
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = shl i64 %x, 7
ret i64 %shl
}
define i64 @shl64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI2-LABEL: shl64p:
; BMI2: # %bb.0:
; BMI2-NEXT: pushl %esi
; BMI2-NEXT: .cfi_def_cfa_offset 8
; BMI2-NEXT: .cfi_offset %esi, -8
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: movl (%eax), %esi
; BMI2-NEXT: movl 4(%eax), %edx
; BMI2-NEXT: shldl %cl, %esi, %edx
; BMI2-NEXT: shlxl %ecx, %esi, %esi
; BMI2-NEXT: xorl %eax, %eax
; BMI2-NEXT: testb $32, %cl
; BMI2-NEXT: cmovnel %esi, %edx
; BMI2-NEXT: cmovel %esi, %eax
; BMI2-NEXT: popl %esi
; BMI2-NEXT: .cfi_def_cfa_offset 4
; BMI2-NEXT: retl
;
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-LABEL: shl64p:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: shlxq %rsi, (%rdi), %rax
; BMI264-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i64, i64* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = shl i64 %x, %shamt
ret i64 %shl
}
define i64 @shl64pi(i64* %p) nounwind uwtable readnone {
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI2-LABEL: shl64pi:
; BMI2: # %bb.0:
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; BMI2-NEXT: movl (%ecx), %eax
; BMI2-NEXT: movl 4(%ecx), %edx
; BMI2-NEXT: shldl $7, %eax, %edx
; BMI2-NEXT: shll $7, %eax
; BMI2-NEXT: retl
;
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-LABEL: shl64pi:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: movq (%rdi), %rax
; BMI264-NEXT: shlq $7, %rax
; BMI264-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i64, i64* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = shl i64 %x, 7
ret i64 %shl
}
define i32 @lshr32(i32 %x, i32 %shamt) nounwind uwtable readnone {
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-LABEL: lshr32:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI2: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; BMI2-NEXT: shrxl %eax, {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: retl
;
; BMI264-LABEL: lshr32:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: shrxl %esi, %edi, %eax
; BMI264-NEXT: retq
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = lshr i32 %x, %shamt
ret i32 %shl
}
define i32 @lshr32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-LABEL: lshr32p:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI2: # %bb.0:
[X86] Add patterns for memory forms of SARX/SHLX/SHRX with careful complexity adjustment to keep shift by immediate using the legacy instructions. These patterns were only missing to favor using the legacy instructions when the shift was a constant. With careful adjustment of the pattern complexity we can make sure the immediate instructions still have priority over these patterns. llvm-svn: 308834
2017-07-23 11:59:37 +08:00
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; BMI2-NEXT: shrxl %ecx, (%eax), %eax
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-NEXT: retl
;
; BMI264-LABEL: lshr32p:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: shrxl %esi, (%rdi), %eax
; BMI264-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i32, i32* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = lshr i32 %x, %shamt
ret i32 %shl
}
define i64 @lshr64(i64 %x, i64 %shamt) nounwind uwtable readnone {
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI2-LABEL: lshr64:
; BMI2: # %bb.0:
; BMI2-NEXT: pushl %esi
; BMI2-NEXT: .cfi_def_cfa_offset 8
; BMI2-NEXT: .cfi_offset %esi, -8
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; BMI2-NEXT: shrdl %cl, %edx, %eax
; BMI2-NEXT: shrxl %ecx, %edx, %esi
; BMI2-NEXT: xorl %edx, %edx
; BMI2-NEXT: testb $32, %cl
; BMI2-NEXT: cmovnel %esi, %eax
; BMI2-NEXT: cmovel %esi, %edx
; BMI2-NEXT: popl %esi
; BMI2-NEXT: .cfi_def_cfa_offset 4
; BMI2-NEXT: retl
;
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-LABEL: lshr64:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: shrxq %rsi, %rdi, %rax
; BMI264-NEXT: retq
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = lshr i64 %x, %shamt
ret i64 %shl
}
define i64 @lshr64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI2-LABEL: lshr64p:
; BMI2: # %bb.0:
; BMI2-NEXT: pushl %esi
; BMI2-NEXT: .cfi_def_cfa_offset 8
; BMI2-NEXT: .cfi_offset %esi, -8
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; BMI2-NEXT: movl (%edx), %eax
; BMI2-NEXT: movl 4(%edx), %edx
; BMI2-NEXT: shrdl %cl, %edx, %eax
; BMI2-NEXT: shrxl %ecx, %edx, %esi
; BMI2-NEXT: xorl %edx, %edx
; BMI2-NEXT: testb $32, %cl
; BMI2-NEXT: cmovnel %esi, %eax
; BMI2-NEXT: cmovel %esi, %edx
; BMI2-NEXT: popl %esi
; BMI2-NEXT: .cfi_def_cfa_offset 4
; BMI2-NEXT: retl
;
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-LABEL: lshr64p:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: shrxq %rsi, (%rdi), %rax
; BMI264-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i64, i64* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = lshr i64 %x, %shamt
ret i64 %shl
}
define i32 @ashr32(i32 %x, i32 %shamt) nounwind uwtable readnone {
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-LABEL: ashr32:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI2: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; BMI2-NEXT: sarxl %eax, {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: retl
;
; BMI264-LABEL: ashr32:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: sarxl %esi, %edi, %eax
; BMI264-NEXT: retq
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = ashr i32 %x, %shamt
ret i32 %shl
}
define i32 @ashr32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-LABEL: ashr32p:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI2: # %bb.0:
[X86] Add patterns for memory forms of SARX/SHLX/SHRX with careful complexity adjustment to keep shift by immediate using the legacy instructions. These patterns were only missing to favor using the legacy instructions when the shift was a constant. With careful adjustment of the pattern complexity we can make sure the immediate instructions still have priority over these patterns. llvm-svn: 308834
2017-07-23 11:59:37 +08:00
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; BMI2-NEXT: sarxl %ecx, (%eax), %eax
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI2-NEXT: retl
;
; BMI264-LABEL: ashr32p:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: sarxl %esi, (%rdi), %eax
; BMI264-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i32, i32* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = ashr i32 %x, %shamt
ret i32 %shl
}
define i64 @ashr64(i64 %x, i64 %shamt) nounwind uwtable readnone {
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI2-LABEL: ashr64:
; BMI2: # %bb.0:
; BMI2-NEXT: pushl %esi
; BMI2-NEXT: .cfi_def_cfa_offset 8
; BMI2-NEXT: .cfi_offset %esi, -8
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; BMI2-NEXT: shrdl %cl, %edx, %eax
; BMI2-NEXT: sarxl %ecx, %edx, %esi
; BMI2-NEXT: sarl $31, %edx
; BMI2-NEXT: testb $32, %cl
; BMI2-NEXT: cmovnel %esi, %eax
; BMI2-NEXT: cmovel %esi, %edx
; BMI2-NEXT: popl %esi
; BMI2-NEXT: .cfi_def_cfa_offset 4
; BMI2-NEXT: retl
;
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-LABEL: ashr64:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: sarxq %rsi, %rdi, %rax
; BMI264-NEXT: retq
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = ashr i64 %x, %shamt
ret i64 %shl
}
define i64 @ashr64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI2-LABEL: ashr64p:
; BMI2: # %bb.0:
; BMI2-NEXT: pushl %esi
; BMI2-NEXT: .cfi_def_cfa_offset 8
; BMI2-NEXT: .cfi_offset %esi, -8
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; BMI2-NEXT: movl (%edx), %eax
; BMI2-NEXT: movl 4(%edx), %edx
; BMI2-NEXT: shrdl %cl, %edx, %eax
; BMI2-NEXT: sarxl %ecx, %edx, %esi
; BMI2-NEXT: sarl $31, %edx
; BMI2-NEXT: testb $32, %cl
; BMI2-NEXT: cmovnel %esi, %eax
; BMI2-NEXT: cmovel %esi, %edx
; BMI2-NEXT: popl %esi
; BMI2-NEXT: .cfi_def_cfa_offset 4
; BMI2-NEXT: retl
;
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-LABEL: ashr64p:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; BMI264-NEXT: sarxq %rsi, (%rdi), %rax
; BMI264-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i64, i64* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = ashr i64 %x, %shamt
ret i64 %shl
}
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
define i32 @shl32and(i32 %t, i32 %val) nounwind {
; BMI2-LABEL: shl32and:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI2: # %bb.0:
[X86] Use SARX/SHLX/SHLX instructions for (shift x (and y, (BitWidth-1))) Fixes PR33841. llvm-svn: 308591
2017-07-20 14:19:55 +08:00
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; BMI2-NEXT: shlxl %eax, {{[0-9]+}}(%esp), %eax
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
; BMI2-NEXT: retl
;
; BMI264-LABEL: shl32and:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Use SARX/SHLX/SHLX instructions for (shift x (and y, (BitWidth-1))) Fixes PR33841. llvm-svn: 308591
2017-07-20 14:19:55 +08:00
; BMI264-NEXT: shlxl %edi, %esi, %eax
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
; BMI264-NEXT: retq
%shamt = and i32 %t, 31
%res = shl i32 %val, %shamt
ret i32 %res
}
define i64 @shl64and(i64 %t, i64 %val) nounwind {
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI2-LABEL: shl64and:
; BMI2: # %bb.0:
; BMI2-NEXT: pushl %esi
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; BMI2-NEXT: shldl %cl, %eax, %edx
; BMI2-NEXT: shlxl %ecx, %eax, %esi
; BMI2-NEXT: xorl %eax, %eax
; BMI2-NEXT: testb $32, %cl
; BMI2-NEXT: cmovnel %esi, %edx
; BMI2-NEXT: cmovel %esi, %eax
; BMI2-NEXT: popl %esi
; BMI2-NEXT: retl
;
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
; BMI264-LABEL: shl64and:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Use SARX/SHLX/SHLX instructions for (shift x (and y, (BitWidth-1))) Fixes PR33841. llvm-svn: 308591
2017-07-20 14:19:55 +08:00
; BMI264-NEXT: shlxq %rdi, %rsi, %rax
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
; BMI264-NEXT: retq
%shamt = and i64 %t, 63
%res = shl i64 %val, %shamt
ret i64 %res
}
define i32 @lshr32and(i32 %t, i32 %val) nounwind {
; BMI2-LABEL: lshr32and:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI2: # %bb.0:
[X86] Use SARX/SHLX/SHLX instructions for (shift x (and y, (BitWidth-1))) Fixes PR33841. llvm-svn: 308591
2017-07-20 14:19:55 +08:00
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; BMI2-NEXT: shrxl %eax, {{[0-9]+}}(%esp), %eax
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
; BMI2-NEXT: retl
;
; BMI264-LABEL: lshr32and:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Use SARX/SHLX/SHLX instructions for (shift x (and y, (BitWidth-1))) Fixes PR33841. llvm-svn: 308591
2017-07-20 14:19:55 +08:00
; BMI264-NEXT: shrxl %edi, %esi, %eax
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
; BMI264-NEXT: retq
%shamt = and i32 %t, 31
%res = lshr i32 %val, %shamt
ret i32 %res
}
define i64 @lshr64and(i64 %t, i64 %val) nounwind {
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI2-LABEL: lshr64and:
; BMI2: # %bb.0:
; BMI2-NEXT: pushl %esi
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; BMI2-NEXT: shrdl %cl, %edx, %eax
; BMI2-NEXT: shrxl %ecx, %edx, %esi
; BMI2-NEXT: xorl %edx, %edx
; BMI2-NEXT: testb $32, %cl
; BMI2-NEXT: cmovnel %esi, %eax
; BMI2-NEXT: cmovel %esi, %edx
; BMI2-NEXT: popl %esi
; BMI2-NEXT: retl
;
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
; BMI264-LABEL: lshr64and:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Use SARX/SHLX/SHLX instructions for (shift x (and y, (BitWidth-1))) Fixes PR33841. llvm-svn: 308591
2017-07-20 14:19:55 +08:00
; BMI264-NEXT: shrxq %rdi, %rsi, %rax
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
; BMI264-NEXT: retq
%shamt = and i64 %t, 63
%res = lshr i64 %val, %shamt
ret i64 %res
}
define i32 @ashr32and(i32 %t, i32 %val) nounwind {
; BMI2-LABEL: ashr32and:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI2: # %bb.0:
[X86] Use SARX/SHLX/SHLX instructions for (shift x (and y, (BitWidth-1))) Fixes PR33841. llvm-svn: 308591
2017-07-20 14:19:55 +08:00
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; BMI2-NEXT: sarxl %eax, {{[0-9]+}}(%esp), %eax
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
; BMI2-NEXT: retl
;
; BMI264-LABEL: ashr32and:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Use SARX/SHLX/SHLX instructions for (shift x (and y, (BitWidth-1))) Fixes PR33841. llvm-svn: 308591
2017-07-20 14:19:55 +08:00
; BMI264-NEXT: sarxl %edi, %esi, %eax
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
; BMI264-NEXT: retq
%shamt = and i32 %t, 31
%res = ashr i32 %val, %shamt
ret i32 %res
}
define i64 @ashr64and(i64 %t, i64 %val) nounwind {
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; BMI2-LABEL: ashr64and:
; BMI2: # %bb.0:
; BMI2-NEXT: pushl %esi
; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; BMI2-NEXT: shrdl %cl, %edx, %eax
; BMI2-NEXT: sarxl %ecx, %edx, %esi
; BMI2-NEXT: sarl $31, %edx
; BMI2-NEXT: testb $32, %cl
; BMI2-NEXT: cmovnel %esi, %eax
; BMI2-NEXT: cmovel %esi, %edx
; BMI2-NEXT: popl %esi
; BMI2-NEXT: retl
;
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
; BMI264-LABEL: ashr64and:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BMI264: # %bb.0:
[X86] Use SARX/SHLX/SHLX instructions for (shift x (and y, (BitWidth-1))) Fixes PR33841. llvm-svn: 308591
2017-07-20 14:19:55 +08:00
; BMI264-NEXT: sarxq %rdi, %rsi, %rax
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test. We should use SHLX and similar instructions for these patterns, but we currently don't. llvm-svn: 308590
2017-07-20 14:19:54 +08:00
; BMI264-NEXT: retq
%shamt = and i64 %t, 63
%res = ashr i64 %val, %shamt
ret i64 %res
}