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llvm-project/llvm/test/CodeGen/X86/avx512-i1test.ll

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AVX-512: Fixed a bug in lowering setcc for MVT::i1 type llvm-svn: 224008
2014-12-11 18:21:12 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; CHECK-LABEL: func
AVX-512: Fixed the "test" operation for i1 type Using KORTESTW for comparison i1 value with zero was wrong since the instruction tests 16 bits. KORTESTW may be used with KSHIFTL+KSHIFTR that clean the 15 upper bits. I removed (X86cmp i1, 0) pattern and zero-extend i1 to i8 and then use TESTB. There are some cases where i1 is in the mask register and the upper bits are already zeroed. Then KORTESTW is the better solution, but it is subject for optimization. Meanwhile, I'm fixing the correctness issue. llvm-svn: 228916
2015-02-12 16:40:34 +08:00
; CHECK: testb
; CHECK: testb
AVX-512: Fixed a bug in lowering setcc for MVT::i1 type llvm-svn: 224008
2014-12-11 18:21:12 +08:00
define void @func() {
bb1:
br i1 undef, label %L_10, label %L_10
L_10: ; preds = %bb1, %bb1
br i1 undef, label %L_30, label %bb56
bb56: ; preds = %L_10
br label %bb33
bb33: ; preds = %bb51, %bb56
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%r111 = load i64, i64* undef, align 8
AVX-512: Fixed a bug in lowering setcc for MVT::i1 type llvm-svn: 224008
2014-12-11 18:21:12 +08:00
br i1 undef, label %bb51, label %bb35
bb35: ; preds = %bb33
br i1 undef, label %L_19, label %bb37
bb37: ; preds = %bb35
%r128 = and i64 %r111, 576460752303423488
%phitmp = icmp eq i64 %r128, 0
br label %L_19
L_19: ; preds = %bb37, %bb35
%"$V_S25.0" = phi i1 [ %phitmp, %bb37 ], [ true, %bb35 ]
br i1 undef, label %bb51, label %bb42
bb42: ; preds = %L_19
%r136 = select i1 %"$V_S25.0", i32* undef, i32* undef
br label %bb51
bb51: ; preds = %bb42, %L_19, %bb33
br i1 false, label %L_30, label %bb33
L_30: ; preds = %bb51, %L_10
ret void
}