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llvm-project/llvm/test/CodeGen/X86/opt_phis2.mir

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[CodeGen] Enhance machine PHIs optimization Summary: Make machine PHIs optimization to work for single value register taken from several different copies. This is the first step to fix PR38917. This change allows to get rid of redundant PHIs (see opt_phis2.mir test) to make the subsequent optimizations (like CSE) possible and simpler. For instance, before this patch the code like this: %b = COPY %z ... %a = PHI %bb1, %a; %bb2, %b could be optimized to: %a = %b but the code like this: %c = COPY %z ... %b = COPY %z ... %a = PHI %bb1, %a; %bb2, %b; %bb3, %c would remain unchanged. With this patch the latter case will be optimized: %a = %z```. Committed on behalf of: Anton Afanasyev anton.a.afanasyev@gmail.com Reviewers: RKSimon, MatzeB Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54839 llvm-svn: 349271
2018-12-15 22:37:01 +08:00
# RUN: llc -run-pass opt-phis -march=x86-64 -o - %s | FileCheck %s
# All PHIs should be removed since they can be securely replaced
# by %8 register.
# CHECK-NOT: PHI
--- |
define void @test() {
ret void
}
...
---
name: test
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 19:16:48 +08:00
alignment: 16
[CodeGen] Enhance machine PHIs optimization Summary: Make machine PHIs optimization to work for single value register taken from several different copies. This is the first step to fix PR38917. This change allows to get rid of redundant PHIs (see opt_phis2.mir test) to make the subsequent optimizations (like CSE) possible and simpler. For instance, before this patch the code like this: %b = COPY %z ... %a = PHI %bb1, %a; %bb2, %b could be optimized to: %a = %b but the code like this: %c = COPY %z ... %b = COPY %z ... %a = PHI %bb1, %a; %bb2, %b; %bb3, %c would remain unchanged. With this patch the latter case will be optimized: %a = %z```. Committed on behalf of: Anton Afanasyev anton.a.afanasyev@gmail.com Reviewers: RKSimon, MatzeB Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54839 llvm-svn: 349271
2018-12-15 22:37:01 +08:00
tracksRegLiveness: true
jumpTable:
kind: block-address
entries:
- id: 0
blocks: [ '%bb.3', '%bb.2', '%bb.1', '%bb.4' ]
body: |
bb.0:
liveins: $edi, $ymm0, $rsi
%9:gr64 = COPY $rsi
%8:vr256 = COPY $ymm0
%7:gr32 = COPY $edi
%11:gr32 = SAR32ri %7, 31, implicit-def dead $eflags
%12:gr32 = SHR32ri %11, 30, implicit-def dead $eflags
%13:gr32 = ADD32rr %7, killed %12, implicit-def dead $eflags
%14:gr32 = AND32ri8 %13, -4, implicit-def dead $eflags
%15:gr32 = SUB32rr %7, %14, implicit-def dead $eflags
%10:gr64_nosp = SUBREG_TO_REG 0, %15, %subreg.sub_32bit
%16:gr32 = SUB32ri8 %15, 3, implicit-def $eflags
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
2019-04-06 03:28:09 +08:00
JCC_1 %bb.8, 7, implicit $eflags
[CodeGen] Enhance machine PHIs optimization Summary: Make machine PHIs optimization to work for single value register taken from several different copies. This is the first step to fix PR38917. This change allows to get rid of redundant PHIs (see opt_phis2.mir test) to make the subsequent optimizations (like CSE) possible and simpler. For instance, before this patch the code like this: %b = COPY %z ... %a = PHI %bb1, %a; %bb2, %b could be optimized to: %a = %b but the code like this: %c = COPY %z ... %b = COPY %z ... %a = PHI %bb1, %a; %bb2, %b; %bb3, %c would remain unchanged. With this patch the latter case will be optimized: %a = %z```. Committed on behalf of: Anton Afanasyev anton.a.afanasyev@gmail.com Reviewers: RKSimon, MatzeB Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54839 llvm-svn: 349271
2018-12-15 22:37:01 +08:00
bb.9:
JMP64m $noreg, 8, %10, %jump-table.0, $noreg :: (load 8 from jump-table)
bb.1:
%0:vr256 = COPY %8
JMP_1 %bb.5
bb.2:
%1:vr256 = COPY %8
JMP_1 %bb.6
bb.3:
%2:vr256 = COPY %8
JMP_1 %bb.7
bb.4:
%3:vr256 = COPY %8
%17:vr128 = VEXTRACTF128rr %8, 1
VPEXTRDmr %9, 1, $noreg, 12, $noreg, killed %17, 2
bb.5:
%4:vr256 = PHI %0, %bb.1, %3, %bb.4
%18:vr128 = VEXTRACTF128rr %4, 1
VPEXTRDmr %9, 1, $noreg, 8, $noreg, killed %18, 1
bb.6:
%5:vr256 = PHI %1, %bb.2, %4, %bb.5
%19:vr128 = VEXTRACTF128rr %5, 1
VMOVPDI2DImr %9, 1, $noreg, 4, $noreg, killed %19
bb.7:
%6:vr256 = PHI %2, %bb.3, %5, %bb.6
%20:vr128 = COPY %6.sub_xmm
VPEXTRDmr %9, 1, $noreg, 0, $noreg, killed %20, 3
bb.8:
RET 0
...