forked from OSchip/llvm-project
34 lines
753 B
LLVM
34 lines
753 B
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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;
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; Check if we generate rounding-asr instruction. It is equivalent to
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; Rd = ((Rs >> #u) +1) >> 1.
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target triple = "hexagon"
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; Function Attrs: nounwind
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define i32 @f0(i32 %a0) #0 {
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b0:
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; CHECK: asr{{.*}}:rnd
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%v0 = alloca i32, align 4
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store i32 %a0, i32* %v0, align 4
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%v1 = load i32, i32* %v0, align 4
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%v2 = ashr i32 %v1, 10
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%v3 = add nsw i32 %v2, 1
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%v4 = ashr i32 %v3, 1
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ret i32 %v4
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}
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; Function Attrs: nounwind
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define i64 @f1(i64 %a0) #0 {
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b0:
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; CHECK: asr{{.*}}:rnd
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%v0 = alloca i64, align 8
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store i64 %a0, i64* %v0, align 8
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%v1 = load i64, i64* %v0, align 8
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%v2 = ashr i64 %v1, 17
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%v3 = add nsw i64 %v2, 1
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%v4 = ashr i64 %v3, 1
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ret i64 %v4
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}
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attributes #0 = { nounwind }
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