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llvm-project/llvm/test/CodeGen/ARM/vstlane.ll

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[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm -mattr=+neon | FileCheck %s
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
Add codegen patterns for VST1-lane instructions. Radar 8599955. llvm-svn: 118176
2010-11-04 00:24:53 +08:00
;Check the (default) alignment.
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vst1lanei8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vst1.8 {d16[3]}, [r0]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i8>, <8 x i8>* %B
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
%tmp2 = extractelement <8 x i8> %tmp1, i32 3
store i8 %tmp2, i8* %A, align 8
Add codegen patterns for VST1-lane instructions. Radar 8599955. llvm-svn: 118176
2010-11-04 00:24:53 +08:00
ret void
}
Add patterns to use post-increment addressing for Neon VST1-lane instructions. llvm-svn: 126477
2011-02-25 14:42:42 +08:00
;Check for a post-increment updating store.
define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst1lanei8_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r2, [r0]
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vst1.8 {d16[3]}, [r2]!
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%A = load i8*, i8** %ptr
%tmp1 = load <8 x i8>, <8 x i8>* %B
Add patterns to use post-increment addressing for Neon VST1-lane instructions. llvm-svn: 126477
2011-02-25 14:42:42 +08:00
%tmp2 = extractelement <8 x i8> %tmp1, i32 3
store i8 %tmp2, i8* %A, align 8
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction One of several parallel first steps to remove the target type of pointers, replacing them with a single opaque pointer type. This adds an explicit type parameter to the gep instruction so that when the first parameter becomes an opaque pointer type, the type to gep through is still available to the instructions. * This doesn't modify gep operators, only instructions (operators will be handled separately) * Textual IR changes only. Bitcode (including upgrade) and changing the in-memory representation will be in separate changes. * geps of vectors are transformed as: getelementptr <4 x float*> %x, ... ->getelementptr float, <4 x float*> %x, ... Then, once the opaque pointer type is introduced, this will ultimately look like: getelementptr float, <4 x ptr> %x with the unambiguous interpretation that it is a vector of pointers to float. * address spaces remain on the pointer, not the type: getelementptr float addrspace(1)* %x ->getelementptr float, float addrspace(1)* %x Then, eventually: getelementptr float, ptr addrspace(1) %x Importantly, the massive amount of test case churn has been automated by same crappy python code. I had to manually update a few test cases that wouldn't fit the script's model (r228970,r229196,r229197,r229198). The python script just massages stdin and writes the result to stdout, I then wrapped that in a shell script to handle replacing files, then using the usual find+xargs to migrate all the files. update.py: import fileinput import sys import re ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") def conv(match, line): if not match: return line line = match.groups()[0] if len(match.groups()[5]) == 0: line += match.groups()[2] line += match.groups()[3] line += ", " line += match.groups()[1] line += "\n" return line for line in sys.stdin: if line.find("getelementptr ") == line.find("getelementptr inbounds"): if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("): line = conv(re.match(ibrep, line), line) elif line.find("getelementptr ") != line.find("getelementptr ("): line = conv(re.match(normrep, line), line) sys.stdout.write(line) apply.sh: for name in "$@" do python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name" rm -f "$name.tmp" done The actual commands: From llvm/src: find test/ -name *.ll | xargs ./apply.sh From llvm/src/tools/clang: find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}" From llvm/src/tools/polly: find test/ -name *.ll | xargs ./apply.sh After that, check-all (with llvm, clang, clang-tools-extra, lld, compiler-rt, and polly all checked out). The extra 'rm' in the apply.sh script is due to a few files in clang's test suite using interesting unicode stuff that my python script was throwing exceptions on. None of those files needed to be migrated, so it seemed sufficient to ignore those cases. Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7636 llvm-svn: 230786
2015-02-28 03:29:02 +08:00
%tmp3 = getelementptr i8, i8* %A, i32 1
Add patterns to use post-increment addressing for Neon VST1-lane instructions. llvm-svn: 126477
2011-02-25 14:42:42 +08:00
store i8* %tmp3, i8** %ptr
ret void
}
Add codegen patterns for VST1-lane instructions. Radar 8599955. llvm-svn: 118176
2010-11-04 00:24:53 +08:00
;Check the alignment value. Max for this instruction is 16 bits:
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: vst1lanei16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vst1.16 {d16[2]}, [r0:16]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i16>, <4 x i16>* %B
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
%tmp2 = extractelement <4 x i16> %tmp1, i32 2
store i16 %tmp2, i16* %A, align 8
Add codegen patterns for VST1-lane instructions. Radar 8599955. llvm-svn: 118176
2010-11-04 00:24:53 +08:00
ret void
}
;Check the alignment value. Max for this instruction is 32 bits:
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: vst1lanei32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vst1.32 {d16[1]}, [r0:32]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <2 x i32>, <2 x i32>* %B
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
%tmp2 = extractelement <2 x i32> %tmp1, i32 1
store i32 %tmp2, i32* %A, align 8
Add codegen patterns for VST1-lane instructions. Radar 8599955. llvm-svn: 118176
2010-11-04 00:24:53 +08:00
ret void
}
Add float patterns for Neon vld1-lane/dup and vst1-lane operations. llvm-svn: 121583
2010-12-11 06:13:32 +08:00
define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst1lanef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vst1.32 {d16[1]}, [r0:32]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <2 x float>, <2 x float>* %B
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
%tmp2 = extractelement <2 x float> %tmp1, i32 1
store float %tmp2, float* %A
Add float patterns for Neon vld1-lane/dup and vst1-lane operations. llvm-svn: 121583
2010-12-11 06:13:32 +08:00
ret void
}
Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain). If there is a store after the load node, then there is a chain, which means that there is another user. Thus, asking hasOneUser would fail. Instead we ask hasNUsesOfValue on the 'data' value. llvm-svn: 131183
2011-05-11 22:40:50 +08:00
; // Can use scalar load. No need to use vectors.
Revert "Tests: Be less dependent on a specific schedule/regalloc" This reverts r192454 Apparently FileCheck isn't as smart as I though and does not enforce a topological order between variable defs+uses. llvm-svn: 192472
2013-10-12 02:09:19 +08:00
; // CHE-CK: vst1.8 {d17[1]}, [r0]
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: vst1laneQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vst1.8 {d17[1]}, [r0]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <16 x i8>, <16 x i8>* %B
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
%tmp2 = extractelement <16 x i8> %tmp1, i32 9
store i8 %tmp2, i8* %A, align 8
Add codegen patterns for VST1-lane instructions. Radar 8599955. llvm-svn: 118176
2010-11-04 00:24:53 +08:00
ret void
}
define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst1laneQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vst1.16 {d17[1]}, [r0:16]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i16>, <8 x i16>* %B
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
%tmp2 = extractelement <8 x i16> %tmp1, i32 5
store i16 %tmp2, i16* %A, align 8
Add codegen patterns for VST1-lane instructions. Radar 8599955. llvm-svn: 118176
2010-11-04 00:24:53 +08:00
ret void
}
Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain). If there is a store after the load node, then there is a chain, which means that there is another user. Thus, asking hasOneUser would fail. Instead we ask hasNUsesOfValue on the 'data' value. llvm-svn: 131183
2011-05-11 22:40:50 +08:00
; // Can use scalar load. No need to use vectors.
Revert "Tests: Be less dependent on a specific schedule/regalloc" This reverts r192454 Apparently FileCheck isn't as smart as I though and does not enforce a topological order between variable defs+uses. llvm-svn: 192472
2013-10-12 02:09:19 +08:00
; // CHE-CK: vst1.32 {d17[1]}, [r0:32]
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: vst1laneQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r1, #12]
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i32>, <4 x i32>* %B
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
%tmp2 = extractelement <4 x i32> %tmp1, i32 3
store i32 %tmp2, i32* %A, align 8
Add codegen patterns for VST1-lane instructions. Radar 8599955. llvm-svn: 118176
2010-11-04 00:24:53 +08:00
ret void
}
Add patterns to use post-increment addressing for Neon VST1-lane instructions. llvm-svn: 126477
2011-02-25 14:42:42 +08:00
;Check for a post-increment updating store.
Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain). If there is a store after the load node, then there is a chain, which means that there is another user. Thus, asking hasOneUser would fail. Instead we ask hasNUsesOfValue on the 'data' value. llvm-svn: 131183
2011-05-11 22:40:50 +08:00
; // Can use scalar load. No need to use vectors.
Revert "Tests: Be less dependent on a specific schedule/regalloc" This reverts r192454 Apparently FileCheck isn't as smart as I though and does not enforce a topological order between variable defs+uses. llvm-svn: 192472
2013-10-12 02:09:19 +08:00
; // CHE-CK: vst1.32 {d17[1]}, [r1:32]!
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
; CHECK-LABEL: vst1laneQi32_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r2, [r0]
; CHECK-NEXT: ldr r1, [r1, #12]
; CHECK-NEXT: str r1, [r2], #4
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%A = load i32*, i32** %ptr
%tmp1 = load <4 x i32>, <4 x i32>* %B
Add patterns to use post-increment addressing for Neon VST1-lane instructions. llvm-svn: 126477
2011-02-25 14:42:42 +08:00
%tmp2 = extractelement <4 x i32> %tmp1, i32 3
store i32 %tmp2, i32* %A, align 8
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction One of several parallel first steps to remove the target type of pointers, replacing them with a single opaque pointer type. This adds an explicit type parameter to the gep instruction so that when the first parameter becomes an opaque pointer type, the type to gep through is still available to the instructions. * This doesn't modify gep operators, only instructions (operators will be handled separately) * Textual IR changes only. Bitcode (including upgrade) and changing the in-memory representation will be in separate changes. * geps of vectors are transformed as: getelementptr <4 x float*> %x, ... ->getelementptr float, <4 x float*> %x, ... Then, once the opaque pointer type is introduced, this will ultimately look like: getelementptr float, <4 x ptr> %x with the unambiguous interpretation that it is a vector of pointers to float. * address spaces remain on the pointer, not the type: getelementptr float addrspace(1)* %x ->getelementptr float, float addrspace(1)* %x Then, eventually: getelementptr float, ptr addrspace(1) %x Importantly, the massive amount of test case churn has been automated by same crappy python code. I had to manually update a few test cases that wouldn't fit the script's model (r228970,r229196,r229197,r229198). The python script just massages stdin and writes the result to stdout, I then wrapped that in a shell script to handle replacing files, then using the usual find+xargs to migrate all the files. update.py: import fileinput import sys import re ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") def conv(match, line): if not match: return line line = match.groups()[0] if len(match.groups()[5]) == 0: line += match.groups()[2] line += match.groups()[3] line += ", " line += match.groups()[1] line += "\n" return line for line in sys.stdin: if line.find("getelementptr ") == line.find("getelementptr inbounds"): if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("): line = conv(re.match(ibrep, line), line) elif line.find("getelementptr ") != line.find("getelementptr ("): line = conv(re.match(normrep, line), line) sys.stdout.write(line) apply.sh: for name in "$@" do python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name" rm -f "$name.tmp" done The actual commands: From llvm/src: find test/ -name *.ll | xargs ./apply.sh From llvm/src/tools/clang: find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}" From llvm/src/tools/polly: find test/ -name *.ll | xargs ./apply.sh After that, check-all (with llvm, clang, clang-tools-extra, lld, compiler-rt, and polly all checked out). The extra 'rm' in the apply.sh script is due to a few files in clang's test suite using interesting unicode stuff that my python script was throwing exceptions on. None of those files needed to be migrated, so it seemed sufficient to ignore those cases. Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7636 llvm-svn: 230786
2015-02-28 03:29:02 +08:00
%tmp3 = getelementptr i32, i32* %A, i32 1
Add patterns to use post-increment addressing for Neon VST1-lane instructions. llvm-svn: 126477
2011-02-25 14:42:42 +08:00
store i32* %tmp3, i32** %ptr
ret void
}
Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain). If there is a store after the load node, then there is a chain, which means that there is another user. Thus, asking hasOneUser would fail. Instead we ask hasNUsesOfValue on the 'data' value. llvm-svn: 131183
2011-05-11 22:40:50 +08:00
; // Can use scalar load. No need to use vectors.
Revert "Tests: Be less dependent on a specific schedule/regalloc" This reverts r192454 Apparently FileCheck isn't as smart as I though and does not enforce a topological order between variable defs+uses. llvm-svn: 192472
2013-10-12 02:09:19 +08:00
; // CHE-CK: vst1.32 {d17[1]}, [r0]
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind {
; CHECK-LABEL: vst1laneQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r1, #12]
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x float>, <4 x float>* %B
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
%tmp2 = extractelement <4 x float> %tmp1, i32 3
store float %tmp2, float* %A
Add float patterns for Neon vld1-lane/dup and vst1-lane operations. llvm-svn: 121583
2010-12-11 06:13:32 +08:00
ret void
}
Support alignment for NEON vld-lane and vst-lane instructions. llvm-svn: 116776
2010-10-19 08:16:32 +08:00
;Check the alignment value. Max for this instruction is 16 bits:
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vst2lanei8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vst2.8 {d16[1], d17[1]}, [r0:16]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i8>, <8 x i8>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst2lane.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
ret void
}
Support alignment for NEON vld-lane and vst-lane instructions. llvm-svn: 116776
2010-10-19 08:16:32 +08:00
;Check the alignment value. Max for this instruction is 32 bits:
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: vst2lanei16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vst2.16 {d16[1], d17[1]}, [r0:32]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast i16* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i16>, <4 x i16>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst2lane.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
ret void
}
Add codegen support for using post-increment NEON load/store instructions. The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. llvm-svn: 125014
2011-02-08 01:43:21 +08:00
;Check for a post-increment updating store with register increment.
define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst2lanei16_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: lsl r1, r2, #1
; CHECK-NEXT: ldr r3, [r0]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vst2.16 {d16[1], d17[1]}, [r3], r1
; CHECK-NEXT: str r3, [r0]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%A = load i16*, i16** %ptr
Add codegen support for using post-increment NEON load/store instructions. The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. llvm-svn: 125014
2011-02-08 01:43:21 +08:00
%tmp0 = bitcast i16* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i16>, <4 x i16>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst2lane.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 2)
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction One of several parallel first steps to remove the target type of pointers, replacing them with a single opaque pointer type. This adds an explicit type parameter to the gep instruction so that when the first parameter becomes an opaque pointer type, the type to gep through is still available to the instructions. * This doesn't modify gep operators, only instructions (operators will be handled separately) * Textual IR changes only. Bitcode (including upgrade) and changing the in-memory representation will be in separate changes. * geps of vectors are transformed as: getelementptr <4 x float*> %x, ... ->getelementptr float, <4 x float*> %x, ... Then, once the opaque pointer type is introduced, this will ultimately look like: getelementptr float, <4 x ptr> %x with the unambiguous interpretation that it is a vector of pointers to float. * address spaces remain on the pointer, not the type: getelementptr float addrspace(1)* %x ->getelementptr float, float addrspace(1)* %x Then, eventually: getelementptr float, ptr addrspace(1) %x Importantly, the massive amount of test case churn has been automated by same crappy python code. I had to manually update a few test cases that wouldn't fit the script's model (r228970,r229196,r229197,r229198). The python script just massages stdin and writes the result to stdout, I then wrapped that in a shell script to handle replacing files, then using the usual find+xargs to migrate all the files. update.py: import fileinput import sys import re ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") def conv(match, line): if not match: return line line = match.groups()[0] if len(match.groups()[5]) == 0: line += match.groups()[2] line += match.groups()[3] line += ", " line += match.groups()[1] line += "\n" return line for line in sys.stdin: if line.find("getelementptr ") == line.find("getelementptr inbounds"): if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("): line = conv(re.match(ibrep, line), line) elif line.find("getelementptr ") != line.find("getelementptr ("): line = conv(re.match(normrep, line), line) sys.stdout.write(line) apply.sh: for name in "$@" do python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name" rm -f "$name.tmp" done The actual commands: From llvm/src: find test/ -name *.ll | xargs ./apply.sh From llvm/src/tools/clang: find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}" From llvm/src/tools/polly: find test/ -name *.ll | xargs ./apply.sh After that, check-all (with llvm, clang, clang-tools-extra, lld, compiler-rt, and polly all checked out). The extra 'rm' in the apply.sh script is due to a few files in clang's test suite using interesting unicode stuff that my python script was throwing exceptions on. None of those files needed to be migrated, so it seemed sufficient to ignore those cases. Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7636 llvm-svn: 230786
2015-02-28 03:29:02 +08:00
%tmp2 = getelementptr i16, i16* %A, i32 %inc
Add codegen support for using post-increment NEON load/store instructions. The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. llvm-svn: 125014
2011-02-08 01:43:21 +08:00
store i16* %tmp2, i16** %ptr
ret void
}
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst2lanei32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vst2.32 {d16[1], d17[1]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast i32* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <2 x i32>, <2 x i32>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst2lane.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
ret void
}
define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst2lanef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vst2.32 {d16[1], d17[1]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast float* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <2 x float>, <2 x float>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst2lane.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
ret void
}
Support alignment for NEON vld-lane and vst-lane instructions. llvm-svn: 116776
2010-10-19 08:16:32 +08:00
;Check the (default) alignment.
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vst2laneQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vst2.16 {d17[1], d19[1]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast i16* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i16>, <8 x i16>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst2lane.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1)
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. llvm-svn: 83596
2009-10-09 07:38:24 +08:00
ret void
}
Support alignment for NEON vld-lane and vst-lane instructions. llvm-svn: 116776
2010-10-19 08:16:32 +08:00
;Check the alignment value. Max for this instruction is 64 bits:
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: vst2laneQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vst2.32 {d17[0], d19[0]}, [r0:64]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast i32* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i32>, <4 x i32>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst2lane.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. llvm-svn: 83596
2009-10-09 07:38:24 +08:00
ret void
}
define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst2laneQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vst2.32 {d17[1], d19[1]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast float* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x float>, <4 x float>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst2lane.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 3, i32 1)
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. llvm-svn: 83596
2009-10-09 07:38:24 +08:00
ret void
}
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
declare void @llvm.arm.neon.vst2lane.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind
declare void @llvm.arm.neon.vst2lane.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind
declare void @llvm.arm.neon.vst2lane.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind
declare void @llvm.arm.neon.vst2lane.p0i8.v2f32(i8*, <2 x float>, <2 x float>, i32, i32) nounwind
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
declare void @llvm.arm.neon.vst2lane.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind
declare void @llvm.arm.neon.vst2lane.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32) nounwind
declare void @llvm.arm.neon.vst2lane.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. llvm-svn: 83596
2009-10-09 07:38:24 +08:00
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst3lanei8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vst3.8 {d16[1], d17[1], d18[1]}, [r0]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i8>, <8 x i8>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst3lane.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
ret void
}
Support alignment for NEON vld-lane and vst-lane instructions. llvm-svn: 116776
2010-10-19 08:16:32 +08:00
;Check the (default) alignment value. VST3 does not support alignment.
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: vst3lanei16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vst3.16 {d16[1], d17[1], d18[1]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast i16* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i16>, <4 x i16>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst3lane.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
ret void
}
define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst3lanei32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vst3.32 {d16[1], d17[1], d18[1]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast i32* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <2 x i32>, <2 x i32>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst3lane.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
ret void
}
define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst3lanef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vst3.32 {d16[1], d17[1], d18[1]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast float* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <2 x float>, <2 x float>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst3lane.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
ret void
}
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. llvm-svn: 83598
2009-10-09 07:51:31 +08:00
define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst3laneQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vorr q10, q8, q8
; CHECK-NEXT: vst3.16 {d17[2], d19[2], d21[2]}, [r0]
; CHECK-NEXT: mov pc, lr
Support alignment for NEON vld-lane and vst-lane instructions. llvm-svn: 116776
2010-10-19 08:16:32 +08:00
;Check the (default) alignment value. VST3 does not support alignment.
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast i16* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i16>, <8 x i16>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst3lane.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6, i32 8)
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. llvm-svn: 83598
2009-10-09 07:51:31 +08:00
ret void
}
define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst3laneQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vorr q10, q8, q8
; CHECK-NEXT: vst3.32 {d16[0], d18[0], d20[0]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast i32* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i32>, <4 x i32>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst3lane.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1)
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. llvm-svn: 83598
2009-10-09 07:51:31 +08:00
ret void
}
Add codegen support for using post-increment NEON load/store instructions. The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. llvm-svn: 125014
2011-02-08 01:43:21 +08:00
;Check for a post-increment updating store.
define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst3laneQi32_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: ldr r2, [r0]
; CHECK-NEXT: vorr q10, q8, q8
; CHECK-NEXT: vst3.32 {d16[0], d18[0], d20[0]}, [r2]!
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%A = load i32*, i32** %ptr
Add codegen support for using post-increment NEON load/store instructions. The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. llvm-svn: 125014
2011-02-08 01:43:21 +08:00
%tmp0 = bitcast i32* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i32>, <4 x i32>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst3lane.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1)
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction One of several parallel first steps to remove the target type of pointers, replacing them with a single opaque pointer type. This adds an explicit type parameter to the gep instruction so that when the first parameter becomes an opaque pointer type, the type to gep through is still available to the instructions. * This doesn't modify gep operators, only instructions (operators will be handled separately) * Textual IR changes only. Bitcode (including upgrade) and changing the in-memory representation will be in separate changes. * geps of vectors are transformed as: getelementptr <4 x float*> %x, ... ->getelementptr float, <4 x float*> %x, ... Then, once the opaque pointer type is introduced, this will ultimately look like: getelementptr float, <4 x ptr> %x with the unambiguous interpretation that it is a vector of pointers to float. * address spaces remain on the pointer, not the type: getelementptr float addrspace(1)* %x ->getelementptr float, float addrspace(1)* %x Then, eventually: getelementptr float, ptr addrspace(1) %x Importantly, the massive amount of test case churn has been automated by same crappy python code. I had to manually update a few test cases that wouldn't fit the script's model (r228970,r229196,r229197,r229198). The python script just massages stdin and writes the result to stdout, I then wrapped that in a shell script to handle replacing files, then using the usual find+xargs to migrate all the files. update.py: import fileinput import sys import re ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") def conv(match, line): if not match: return line line = match.groups()[0] if len(match.groups()[5]) == 0: line += match.groups()[2] line += match.groups()[3] line += ", " line += match.groups()[1] line += "\n" return line for line in sys.stdin: if line.find("getelementptr ") == line.find("getelementptr inbounds"): if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("): line = conv(re.match(ibrep, line), line) elif line.find("getelementptr ") != line.find("getelementptr ("): line = conv(re.match(normrep, line), line) sys.stdout.write(line) apply.sh: for name in "$@" do python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name" rm -f "$name.tmp" done The actual commands: From llvm/src: find test/ -name *.ll | xargs ./apply.sh From llvm/src/tools/clang: find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}" From llvm/src/tools/polly: find test/ -name *.ll | xargs ./apply.sh After that, check-all (with llvm, clang, clang-tools-extra, lld, compiler-rt, and polly all checked out). The extra 'rm' in the apply.sh script is due to a few files in clang's test suite using interesting unicode stuff that my python script was throwing exceptions on. None of those files needed to be migrated, so it seemed sufficient to ignore those cases. Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7636 llvm-svn: 230786
2015-02-28 03:29:02 +08:00
%tmp2 = getelementptr i32, i32* %A, i32 3
Add codegen support for using post-increment NEON load/store instructions. The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. llvm-svn: 125014
2011-02-08 01:43:21 +08:00
store i32* %tmp2, i32** %ptr
ret void
}
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. llvm-svn: 83598
2009-10-09 07:51:31 +08:00
define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst3laneQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vorr q10, q8, q8
; CHECK-NEXT: vst3.32 {d16[1], d18[1], d20[1]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast float* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x float>, <4 x float>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst3lane.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. llvm-svn: 83598
2009-10-09 07:51:31 +08:00
ret void
}
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
declare void @llvm.arm.neon.vst3lane.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind
declare void @llvm.arm.neon.vst3lane.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind
declare void @llvm.arm.neon.vst3lane.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
declare void @llvm.arm.neon.vst3lane.p0i8.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
declare void @llvm.arm.neon.vst3lane.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind
declare void @llvm.arm.neon.vst3lane.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind
declare void @llvm.arm.neon.vst3lane.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. llvm-svn: 83598
2009-10-09 07:51:31 +08:00
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
Support alignment for NEON vld-lane and vst-lane instructions. llvm-svn: 116776
2010-10-19 08:16:32 +08:00
;Check the alignment value. Max for this instruction is 32 bits:
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vst4lanei8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vorr d19, d16, d16
; CHECK-NEXT: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i8>, <8 x i8>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst4lane.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
ret void
}
Add codegen support for using post-increment NEON load/store instructions. The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. llvm-svn: 125014
2011-02-08 01:43:21 +08:00
;Check for a post-increment updating store.
define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst4lanei8_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: ldr r2, [r0]
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vorr d19, d16, d16
; CHECK-NEXT: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r2:32]!
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%A = load i8*, i8** %ptr
%tmp1 = load <8 x i8>, <8 x i8>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst4lane.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction One of several parallel first steps to remove the target type of pointers, replacing them with a single opaque pointer type. This adds an explicit type parameter to the gep instruction so that when the first parameter becomes an opaque pointer type, the type to gep through is still available to the instructions. * This doesn't modify gep operators, only instructions (operators will be handled separately) * Textual IR changes only. Bitcode (including upgrade) and changing the in-memory representation will be in separate changes. * geps of vectors are transformed as: getelementptr <4 x float*> %x, ... ->getelementptr float, <4 x float*> %x, ... Then, once the opaque pointer type is introduced, this will ultimately look like: getelementptr float, <4 x ptr> %x with the unambiguous interpretation that it is a vector of pointers to float. * address spaces remain on the pointer, not the type: getelementptr float addrspace(1)* %x ->getelementptr float, float addrspace(1)* %x Then, eventually: getelementptr float, ptr addrspace(1) %x Importantly, the massive amount of test case churn has been automated by same crappy python code. I had to manually update a few test cases that wouldn't fit the script's model (r228970,r229196,r229197,r229198). The python script just massages stdin and writes the result to stdout, I then wrapped that in a shell script to handle replacing files, then using the usual find+xargs to migrate all the files. update.py: import fileinput import sys import re ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") def conv(match, line): if not match: return line line = match.groups()[0] if len(match.groups()[5]) == 0: line += match.groups()[2] line += match.groups()[3] line += ", " line += match.groups()[1] line += "\n" return line for line in sys.stdin: if line.find("getelementptr ") == line.find("getelementptr inbounds"): if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("): line = conv(re.match(ibrep, line), line) elif line.find("getelementptr ") != line.find("getelementptr ("): line = conv(re.match(normrep, line), line) sys.stdout.write(line) apply.sh: for name in "$@" do python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name" rm -f "$name.tmp" done The actual commands: From llvm/src: find test/ -name *.ll | xargs ./apply.sh From llvm/src/tools/clang: find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}" From llvm/src/tools/polly: find test/ -name *.ll | xargs ./apply.sh After that, check-all (with llvm, clang, clang-tools-extra, lld, compiler-rt, and polly all checked out). The extra 'rm' in the apply.sh script is due to a few files in clang's test suite using interesting unicode stuff that my python script was throwing exceptions on. None of those files needed to be migrated, so it seemed sufficient to ignore those cases. Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7636 llvm-svn: 230786
2015-02-28 03:29:02 +08:00
%tmp2 = getelementptr i8, i8* %A, i32 4
Add codegen support for using post-increment NEON load/store instructions. The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. llvm-svn: 125014
2011-02-08 01:43:21 +08:00
store i8* %tmp2, i8** %ptr
ret void
}
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst4lanei16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vorr d19, d16, d16
; CHECK-NEXT: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast i16* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i16>, <4 x i16>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst4lane.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1)
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
ret void
}
Support alignment for NEON vld-lane and vst-lane instructions. llvm-svn: 116776
2010-10-19 08:16:32 +08:00
;Check the alignment value. Max for this instruction is 128 bits:
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: vst4lanei32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vorr d19, d16, d16
; CHECK-NEXT: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast i32* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <2 x i32>, <2 x i32>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst4lane.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16)
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
ret void
}
define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst4lanef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vorr d19, d16, d16
; CHECK-NEXT: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast float* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <2 x float>, <2 x float>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst4lane.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
Add support for generating code for vst{234}lane intrinsics. llvm-svn: 80707
2009-09-02 02:51:56 +08:00
ret void
}
Support alignment for NEON vld-lane and vst-lane instructions. llvm-svn: 116776
2010-10-19 08:16:32 +08:00
;Check the alignment value. Max for this instruction is 64 bits:
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vst4laneQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vorr q10, q8, q8
; CHECK-NEXT: vorr q11, q8, q8
; CHECK-NEXT: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast i16* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i16>, <8 x i16>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst4lane.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16)
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. llvm-svn: 83600
2009-10-09 08:01:36 +08:00
ret void
}
Support alignment for NEON vld-lane and vst-lane instructions. llvm-svn: 116776
2010-10-19 08:16:32 +08:00
;Check the (default) alignment.
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: vst4laneQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vorr q10, q8, q8
; CHECK-NEXT: vorr q11, q8, q8
; CHECK-NEXT: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast i32* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i32>, <4 x i32>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst4lane.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1)
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. llvm-svn: 83600
2009-10-09 08:01:36 +08:00
ret void
}
define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: vst4laneQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vorr q10, q8, q8
; CHECK-NEXT: vorr q11, q8, q8
; CHECK-NEXT: vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r0]
; CHECK-NEXT: mov pc, lr
Fix tests for Neon load/store intrinsics to match the i8* types expected by the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840
2010-04-20 08:17:16 +08:00
%tmp0 = bitcast float* %A to i8*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x float>, <4 x float>* %B
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
call void @llvm.arm.neon.vst4lane.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. llvm-svn: 83600
2009-10-09 08:01:36 +08:00
ret void
}
Don't crash on variable insertelement on ARM. PR10258. llvm-svn: 142871
2011-10-25 07:08:52 +08:00
; Make sure this doesn't crash; PR10258
define <8 x i16> @variable_insertelement(<8 x i16> %a, i16 %b, i32 %c) nounwind readnone {
[ARM] Regenerate vector lane store tests
2019-11-19 21:18:31 +08:00
; CHECK-LABEL: variable_insertelement:
; CHECK: @ %bb.0:
; CHECK-NEXT: push {r11, lr}
; CHECK-NEXT: mov r11, sp
; CHECK-NEXT: sub sp, sp, #24
; CHECK-NEXT: bic sp, sp, #15
; CHECK-NEXT: ldr lr, [r11, #12]
; CHECK-NEXT: vmov d17, r2, r3
; CHECK-NEXT: vmov d16, r0, r1
; CHECK-NEXT: mov r1, sp
; CHECK-NEXT: and r0, lr, #7
; CHECK-NEXT: mov r2, r1
; CHECK-NEXT: ldrh r12, [r11, #8]
; CHECK-NEXT: lsl r0, r0, #1
; CHECK-NEXT: vst1.64 {d16, d17}, [r2:128], r0
; CHECK-NEXT: strh r12, [r2]
; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov sp, r11
; CHECK-NEXT: pop {r11, lr}
; CHECK-NEXT: mov pc, lr
Don't crash on variable insertelement on ARM. PR10258. llvm-svn: 142871
2011-10-25 07:08:52 +08:00
%r = insertelement <8 x i16> %a, i16 %b, i32 %c
ret <8 x i16> %r
}
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
declare void @llvm.arm.neon.vst4lane.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind
declare void @llvm.arm.neon.vst4lane.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind
declare void @llvm.arm.neon.vst4lane.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
declare void @llvm.arm.neon.vst4lane.p0i8.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. llvm-svn: 83600
2009-10-09 08:01:36 +08:00
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
2015-09-30 18:56:37 +08:00
declare void @llvm.arm.neon.vst4lane.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind
declare void @llvm.arm.neon.vst4lane.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind
declare void @llvm.arm.neon.vst4lane.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind