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llvm-project/llvm/test/CodeGen/ARM/useaa.ll

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[ARM] Enable useAA() for the in-order Cortex-R52 This option allows codegen (such as DAGCombine or MI scheduling) to use alias analysis information, which can help with the codegen on in-order cpu's, especially machine scheduling. Here I have done things the same way as AArch64, adding a subtarget feature to enable this for specific cores, and enabled it for the R52 where we have a schedule to make use of it. Differential Revision: https://reviews.llvm.org/D48074 llvm-svn: 335249
2018-06-21 23:48:29 +08:00
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
[ARM] Cortex-M4 schedule This patch adds a simple Cortex-M4 schedule, renaming the existing M3 schedule to M4 and filling in the latencies as-per the Cortex-M4 TRM: https://developer.arm.com/docs/ddi0439/latest Most of these are 1, with the important exception being loads taking 2 cycles. A few others are also higher, but I don't believe they make a large difference. I've repurposed the M3 schedule as the latencies are mostly the same between the two cores, with the M4 having more FP and DSP instructions. We also turn on MISched and UseAA for the cores that now use this. It also adds some schedule Write's to various instruction to make things simpler. Differential Revision: https://reviews.llvm.org/D54142 llvm-svn: 360768
2019-05-15 20:41:58 +08:00
; RUN: llc < %s -mtriple=armv7m-eabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
; RUN: llc < %s -mtriple=armv8m-eabi -mcpu=cortex-m33 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
[ARM] Enable useAA() for the in-order Cortex-R52 This option allows codegen (such as DAGCombine or MI scheduling) to use alias analysis information, which can help with the codegen on in-order cpu's, especially machine scheduling. Here I have done things the same way as AArch64, adding a subtarget feature to enable this for specific cores, and enabled it for the R52 where we have a schedule to make use of it. Differential Revision: https://reviews.llvm.org/D48074 llvm-svn: 335249
2018-06-21 23:48:29 +08:00
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
; Check we use AA during codegen, so can interleave these loads/stores.
; CHECK-LABEL: test
; GENERIC: ldr
; GENERIC: ldr
; GENERIC: str
[ARM] Always enable UseAA in the arm backend This feature controls whether AA is used into the backend, and was previously turned on for certain subtargets to help create less constrained scheduling graphs. This patch turns it on for all subtargets, so that they can all make use of the extra information to produce better code. Differential Revision: https://reviews.llvm.org/D69796
2019-11-05 18:46:56 +08:00
; GENERIC: str
[ARM] Enable useAA() for the in-order Cortex-R52 This option allows codegen (such as DAGCombine or MI scheduling) to use alias analysis information, which can help with the codegen on in-order cpu's, especially machine scheduling. Here I have done things the same way as AArch64, adding a subtarget feature to enable this for specific cores, and enabled it for the R52 where we have a schedule to make use of it. Differential Revision: https://reviews.llvm.org/D48074 llvm-svn: 335249
2018-06-21 23:48:29 +08:00
; USEAA: ldr
; USEAA: ldr
; USEAA: str
; USEAA: str
define void @test(i32* nocapture %a, i32* noalias nocapture %b) {
entry:
%0 = load i32, i32* %a, align 4
%add = add nsw i32 %0, 10
store i32 %add, i32* %a, align 4
%1 = load i32, i32* %b, align 4
%add2 = add nsw i32 %1, 20
store i32 %add2, i32* %b, align 4
ret void
}