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llvm-project/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll

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Revert the test moves from 176733. Use "REQUIRES: asserts" instead. llvm-svn: 176873
2013-03-13 00:27:52 +08:00
; REQUIRES: asserts
Convert the uses of '|&' to use '2>&1 |' instead, which works on old versions of Bash. In addition, I can back out the change to the lit built-in shell test runner to support this. This should fix the majority of fallout on Darwin, but I suspect there will be a few straggling issues. llvm-svn: 159544
2012-07-03 02:37:59 +08:00
; RUN: llc < %s -o /dev/null -stats 2>&1 | FileCheck %s -check-prefix=STATS
Do not sink instruction, if it is not profitable. On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. llvm-svn: 146604
2011-12-15 07:20:38 +08:00
; Radar 10266272
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-apple-ios4.0.0"
; STATS-NOT: machine-sink
Improve test robustness Improve test robustness in preparation of coming commits: - Avoid undefs which may get propagated too much. - Remove several pointless add 0, instructions llvm-svn: 231307
2015-03-05 06:31:18 +08:00
define i32 @foo(i32 %h, i32 %arg1) nounwind readonly ssp {
Do not sink instruction, if it is not profitable. On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. llvm-svn: 146604
2011-12-15 07:20:38 +08:00
entry:
br label %for.cond
for.cond: ; preds = %for.body, %entry
%cmp = icmp slt i32 0, %h
br i1 %cmp, label %for.body, label %if.end299
for.body: ; preds = %for.cond
Improve test robustness Improve test robustness in preparation of coming commits: - Avoid undefs which may get propagated too much. - Remove several pointless add 0, instructions llvm-svn: 231307
2015-03-05 06:31:18 +08:00
%cond0 = icmp ne i32 %arg1, 42
%v.5 = select i1 %cond0, i32 undef, i32 0
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i8, i8* undef, align 1
Do not sink instruction, if it is not profitable. On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. llvm-svn: 146604
2011-12-15 07:20:38 +08:00
%conv88 = zext i8 %0 to i32
%sub89 = sub nsw i32 0, %conv88
Improve test robustness Improve test robustness in preparation of coming commits: - Avoid undefs which may get propagated too much. - Remove several pointless add 0, instructions llvm-svn: 231307
2015-03-05 06:31:18 +08:00
%cond1 = icmp ne i32 %arg1, 23
%v.8 = select i1 %cond1, i32 undef, i32 %sub89
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%1 = load i8, i8* null, align 1
Do not sink instruction, if it is not profitable. On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. llvm-svn: 146604
2011-12-15 07:20:38 +08:00
%conv108 = zext i8 %1 to i32
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%2 = load i8, i8* undef, align 1
Do not sink instruction, if it is not profitable. On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. llvm-svn: 146604
2011-12-15 07:20:38 +08:00
%conv110 = zext i8 %2 to i32
%sub111 = sub nsw i32 %conv108, %conv110
%cmp112 = icmp slt i32 %sub111, 0
%sub115 = sub nsw i32 0, %sub111
Improve test robustness Improve test robustness in preparation of coming commits: - Avoid undefs which may get propagated too much. - Remove several pointless add 0, instructions llvm-svn: 231307
2015-03-05 06:31:18 +08:00
%abs = select i1 %cmp112, i32 %sub115, i32 %sub111
%add95 = add i32 %v.5, %v.8
%add117 = add i32 %add95, %abs
Do not sink instruction, if it is not profitable. On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. llvm-svn: 146604
2011-12-15 07:20:38 +08:00
br i1 undef, label %for.cond, label %if.end299
if.end299: ; preds = %for.body, %for.cond
Improve test robustness Improve test robustness in preparation of coming commits: - Avoid undefs which may get propagated too much. - Remove several pointless add 0, instructions llvm-svn: 231307
2015-03-05 06:31:18 +08:00
%s.10 = phi i32 [ %add117, %for.body ], [ 0, %for.cond ]
Do not sink instruction, if it is not profitable. On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. llvm-svn: 146604
2011-12-15 07:20:38 +08:00
ret i32 %s.10
}