2005-11-15 08:40:23 +08:00
|
|
|
//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-30 04:36:04 +08:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2005-11-15 08:40:23 +08:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file defines the interfaces that X86 uses to lower LLVM code into a
|
|
|
|
// selection DAG.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#ifndef X86ISELLOWERING_H
|
|
|
|
#define X86ISELLOWERING_H
|
|
|
|
|
2008-01-06 00:56:59 +08:00
|
|
|
#include "X86MachineFunctionInfo.h"
|
2012-12-04 15:12:27 +08:00
|
|
|
#include "X86RegisterInfo.h"
|
|
|
|
#include "X86Subtarget.h"
|
|
|
|
#include "llvm/CodeGen/CallingConvLower.h"
|
2008-09-03 10:54:11 +08:00
|
|
|
#include "llvm/CodeGen/FastISel.h"
|
2005-11-15 08:40:23 +08:00
|
|
|
#include "llvm/CodeGen/SelectionDAG.h"
|
2012-12-04 15:12:27 +08:00
|
|
|
#include "llvm/Target/TargetLowering.h"
|
|
|
|
#include "llvm/Target/TargetOptions.h"
|
2005-11-15 08:40:23 +08:00
|
|
|
|
|
|
|
namespace llvm {
|
|
|
|
namespace X86ISD {
|
2006-01-06 08:43:03 +08:00
|
|
|
// X86 Specific DAG Nodes
|
2005-11-15 08:40:23 +08:00
|
|
|
enum NodeType {
|
|
|
|
// Start the numbering where the builtin ops leave off.
|
2008-09-24 02:42:32 +08:00
|
|
|
FIRST_NUMBER = ISD::BUILTIN_OP_END,
|
2005-11-15 08:40:23 +08:00
|
|
|
|
2007-12-14 10:13:44 +08:00
|
|
|
/// BSF - Bit scan forward.
|
|
|
|
/// BSR - Bit scan reverse.
|
|
|
|
BSF,
|
|
|
|
BSR,
|
|
|
|
|
2006-01-10 02:33:28 +08:00
|
|
|
/// SHLD, SHRD - Double shift instructions. These correspond to
|
|
|
|
/// X86::SHLDxx and X86::SHRDxx instructions.
|
|
|
|
SHLD,
|
|
|
|
SHRD,
|
|
|
|
|
2006-01-31 11:14:29 +08:00
|
|
|
/// FAND - Bitwise logical AND of floating point values. This corresponds
|
|
|
|
/// to X86::ANDPS or X86::ANDPD.
|
|
|
|
FAND,
|
|
|
|
|
2007-01-05 15:55:56 +08:00
|
|
|
/// FOR - Bitwise logical OR of floating point values. This corresponds
|
|
|
|
/// to X86::ORPS or X86::ORPD.
|
|
|
|
FOR,
|
|
|
|
|
2006-02-01 06:28:30 +08:00
|
|
|
/// FXOR - Bitwise logical XOR of floating point values. This corresponds
|
|
|
|
/// to X86::XORPS or X86::XORPD.
|
|
|
|
FXOR,
|
|
|
|
|
2013-08-08 23:19:25 +08:00
|
|
|
/// FANDN - Bitwise logical ANDNOT of floating point values. This
|
X86: Turn fp selects into mask operations.
double test(double a, double b, double c, double d) { return a<b ? c : d; }
before:
_test:
ucomisd %xmm0, %xmm1
ja LBB0_2
movaps %xmm3, %xmm2
LBB0_2:
movaps %xmm2, %xmm0
after:
_test:
cmpltsd %xmm1, %xmm0
andpd %xmm0, %xmm2
andnpd %xmm3, %xmm0
orpd %xmm2, %xmm0
Small speedup on Benchmarks/SmallPT
llvm-svn: 187706
2013-08-04 20:05:16 +08:00
|
|
|
/// corresponds to X86::ANDNPS or X86::ANDNPD.
|
|
|
|
FANDN,
|
|
|
|
|
2007-01-06 05:37:56 +08:00
|
|
|
/// FSRL - Bitwise logical right shift of floating point values. These
|
|
|
|
/// corresponds to X86::PSRLDQ.
|
2007-01-05 15:55:56 +08:00
|
|
|
FSRL,
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
/// CALL - These operations represent an abstract X86 call
|
2005-11-15 08:40:23 +08:00
|
|
|
/// instruction, which includes a bunch of information. In particular the
|
|
|
|
/// operands of these node are:
|
|
|
|
///
|
|
|
|
/// #0 - The incoming token chain
|
|
|
|
/// #1 - The callee
|
|
|
|
/// #2 - The number of arg bytes the caller pushes on the stack.
|
|
|
|
/// #3 - The number of arg bytes the callee pops off the stack.
|
|
|
|
/// #4 - The value to pass in AL/AX/EAX (optional)
|
|
|
|
/// #5 - The value to pass in DL/DX/EDX (optional)
|
|
|
|
///
|
|
|
|
/// The result values of these nodes are:
|
|
|
|
///
|
|
|
|
/// #0 - The outgoing token chain
|
|
|
|
/// #1 - The first register result value (optional)
|
|
|
|
/// #2 - The second register result value (optional)
|
|
|
|
///
|
|
|
|
CALL,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
2010-10-21 07:40:27 +08:00
|
|
|
/// RDTSC_DAG - This operation implements the lowering for
|
2005-11-21 05:41:10 +08:00
|
|
|
/// readcyclecounter
|
|
|
|
RDTSC_DAG,
|
2005-12-17 09:21:05 +08:00
|
|
|
|
|
|
|
/// X86 compare and logical compare instructions.
|
2007-09-18 01:42:53 +08:00
|
|
|
CMP, COMI, UCOMI,
|
2005-12-17 09:21:05 +08:00
|
|
|
|
2008-12-24 06:45:23 +08:00
|
|
|
/// X86 bit-test instructions.
|
|
|
|
BT,
|
|
|
|
|
2010-12-20 08:59:46 +08:00
|
|
|
/// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
|
|
|
|
/// operand, usually produced by a CMP instruction.
|
2005-12-22 04:21:51 +08:00
|
|
|
SETCC,
|
|
|
|
|
2009-12-15 08:53:42 +08:00
|
|
|
// Same as SETCC except it's materialized with a sbb and the value is all
|
|
|
|
// one's or all zero's.
|
2010-12-20 06:08:31 +08:00
|
|
|
SETCC_CARRY, // R = carry_bit ? ~0 : 0
|
2009-12-15 08:53:42 +08:00
|
|
|
|
2011-06-04 07:53:54 +08:00
|
|
|
/// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
|
|
|
|
/// Operands are two FP values to compare; result is a mask of
|
|
|
|
/// 0s or 1s. Generally DTRT for C/C++ with NaNs.
|
|
|
|
FSETCCss, FSETCCsd,
|
|
|
|
|
2011-06-01 12:39:42 +08:00
|
|
|
/// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
|
|
|
|
/// result in an integer GPR. Needs masking for scalar result.
|
|
|
|
FGETSIGNx86,
|
|
|
|
|
2009-03-12 14:46:02 +08:00
|
|
|
/// X86 conditional moves. Operand 0 and operand 1 are the two values
|
|
|
|
/// to select from. Operand 2 is the condition code, and operand 3 is the
|
|
|
|
/// flag operand produced by a CMP or TEST instruction. It also writes a
|
|
|
|
/// flag result.
|
2005-12-17 09:21:05 +08:00
|
|
|
CMOV,
|
2005-12-20 07:12:38 +08:00
|
|
|
|
2009-03-23 23:40:10 +08:00
|
|
|
/// X86 conditional branches. Operand 0 is the chain operand, operand 1
|
|
|
|
/// is the block to branch if condition is true, operand 2 is the
|
|
|
|
/// condition code, and operand 3 is the flag operand produced by a CMP
|
2005-12-22 04:21:51 +08:00
|
|
|
/// or TEST instruction.
|
2005-12-20 07:12:38 +08:00
|
|
|
BRCOND,
|
2005-12-21 10:39:21 +08:00
|
|
|
|
2009-03-23 23:40:10 +08:00
|
|
|
/// Return with a flag operand. Operand 0 is the chain operand, operand
|
|
|
|
/// 1 is the number of bytes of stack to pop.
|
2005-12-21 10:39:21 +08:00
|
|
|
RET_FLAG,
|
2006-01-12 06:15:48 +08:00
|
|
|
|
|
|
|
/// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
|
|
|
|
REP_STOS,
|
|
|
|
|
|
|
|
/// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
|
|
|
|
REP_MOVS,
|
2006-02-01 06:28:30 +08:00
|
|
|
|
2006-02-18 08:15:05 +08:00
|
|
|
/// GlobalBaseReg - On Darwin, this node represents the result of the popl
|
|
|
|
/// at function entry, used for PIC code.
|
|
|
|
GlobalBaseReg,
|
2006-02-23 10:43:52 +08:00
|
|
|
|
2008-09-17 05:48:12 +08:00
|
|
|
/// Wrapper - A wrapper node for TargetConstantPool,
|
|
|
|
/// TargetExternalSymbol, and TargetGlobalAddress.
|
2006-02-24 04:41:18 +08:00
|
|
|
Wrapper,
|
2006-03-22 07:01:21 +08:00
|
|
|
|
2006-12-01 05:55:46 +08:00
|
|
|
/// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
|
|
|
|
/// relative displacements.
|
|
|
|
WrapperRIP,
|
|
|
|
|
2010-10-01 07:57:10 +08:00
|
|
|
/// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
|
|
|
|
/// to an MMX vector. If you think this is too close to the previous
|
|
|
|
/// mnemonic, so do I; blame Intel.
|
|
|
|
MOVDQ2Q,
|
|
|
|
|
2012-10-31 06:15:38 +08:00
|
|
|
/// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
|
|
|
|
/// vector to a GPR.
|
|
|
|
MMX_MOVD2W,
|
|
|
|
|
2008-02-11 12:19:36 +08:00
|
|
|
/// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
|
|
|
|
/// i32, corresponds to X86::PEXTRB.
|
|
|
|
PEXTRB,
|
|
|
|
|
2006-04-01 03:22:53 +08:00
|
|
|
/// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
|
2006-04-01 05:55:24 +08:00
|
|
|
/// i32, corresponds to X86::PEXTRW.
|
2006-04-01 03:22:53 +08:00
|
|
|
PEXTRW,
|
2006-04-01 05:55:24 +08:00
|
|
|
|
2008-02-11 12:19:36 +08:00
|
|
|
/// INSERTPS - Insert any element of a 4 x float vector into any element
|
|
|
|
/// of a destination 4 x floatvector.
|
|
|
|
INSERTPS,
|
|
|
|
|
|
|
|
/// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
|
|
|
|
/// corresponds to X86::PINSRB.
|
|
|
|
PINSRB,
|
|
|
|
|
2006-04-01 05:55:24 +08:00
|
|
|
/// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
|
|
|
|
/// corresponds to X86::PINSRW.
|
2010-02-23 10:07:48 +08:00
|
|
|
PINSRW, MMX_PINSRW,
|
2006-11-11 05:43:37 +08:00
|
|
|
|
Generate better code for v8i16 shuffles on SSE2
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
cleanups.
New tests that test the above.
Examples:
New:
_shuf2:
pextrw $7, %xmm0, %eax
punpcklqdq %xmm1, %xmm0
pshuflw $128, %xmm0, %xmm0
pinsrw $2, %eax, %xmm0
Old:
_shuf2:
pextrw $2, %xmm0, %eax
pextrw $7, %xmm0, %ecx
pinsrw $2, %ecx, %xmm0
pinsrw $3, %eax, %xmm0
movd %xmm1, %eax
pinsrw $4, %eax, %xmm0
ret
=========
New:
_shuf4:
punpcklqdq %xmm1, %xmm0
pshufb LCPI1_0, %xmm0
Old:
_shuf4:
pextrw $3, %xmm0, %eax
movsd %xmm1, %xmm0
pextrw $3, %xmm1, %ecx
pinsrw $4, %ecx, %xmm0
pinsrw $5, %eax, %xmm0
========
New:
_shuf1:
pushl %ebx
pushl %edi
pushl %esi
pextrw $1, %xmm0, %eax
rolw $8, %ax
movd %xmm0, %ecx
rolw $8, %cx
pextrw $5, %xmm0, %edx
pextrw $4, %xmm0, %esi
pextrw $3, %xmm0, %edi
pextrw $2, %xmm0, %ebx
movaps %xmm0, %xmm1
pinsrw $0, %ecx, %xmm1
pinsrw $1, %eax, %xmm1
rolw $8, %bx
pinsrw $2, %ebx, %xmm1
rolw $8, %di
pinsrw $3, %edi, %xmm1
rolw $8, %si
pinsrw $4, %esi, %xmm1
rolw $8, %dx
pinsrw $5, %edx, %xmm1
pextrw $7, %xmm0, %eax
rolw $8, %ax
movaps %xmm1, %xmm0
pinsrw $7, %eax, %xmm0
popl %esi
popl %edi
popl %ebx
ret
Old:
_shuf1:
subl $252, %esp
movaps %xmm0, (%esp)
movaps %xmm0, 16(%esp)
movaps %xmm0, 32(%esp)
movaps %xmm0, 48(%esp)
movaps %xmm0, 64(%esp)
movaps %xmm0, 80(%esp)
movaps %xmm0, 96(%esp)
movaps %xmm0, 224(%esp)
movaps %xmm0, 208(%esp)
movaps %xmm0, 192(%esp)
movaps %xmm0, 176(%esp)
movaps %xmm0, 160(%esp)
movaps %xmm0, 144(%esp)
movaps %xmm0, 128(%esp)
movaps %xmm0, 112(%esp)
movzbl 14(%esp), %eax
movd %eax, %xmm1
movzbl 22(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm1, %xmm2
movzbl 42(%esp), %eax
movd %eax, %xmm1
movzbl 50(%esp), %eax
movd %eax, %xmm3
punpcklbw %xmm1, %xmm3
punpcklbw %xmm2, %xmm3
movzbl 77(%esp), %eax
movd %eax, %xmm1
movzbl 84(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm1, %xmm2
movzbl 104(%esp), %eax
movd %eax, %xmm1
punpcklbw %xmm1, %xmm0
punpcklbw %xmm2, %xmm0
movaps %xmm0, %xmm1
punpcklbw %xmm3, %xmm1
movzbl 127(%esp), %eax
movd %eax, %xmm0
movzbl 135(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm0, %xmm2
movzbl 155(%esp), %eax
movd %eax, %xmm0
movzbl 163(%esp), %eax
movd %eax, %xmm3
punpcklbw %xmm0, %xmm3
punpcklbw %xmm2, %xmm3
movzbl 188(%esp), %eax
movd %eax, %xmm0
movzbl 197(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm0, %xmm2
movzbl 217(%esp), %eax
movd %eax, %xmm4
movzbl 225(%esp), %eax
movd %eax, %xmm0
punpcklbw %xmm4, %xmm0
punpcklbw %xmm2, %xmm0
punpcklbw %xmm3, %xmm0
punpcklbw %xmm1, %xmm0
addl $252, %esp
ret
llvm-svn: 65311
2009-02-23 16:49:38 +08:00
|
|
|
/// PSHUFB - Shuffle 16 8-bit values within a vector.
|
|
|
|
PSHUFB,
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2011-07-14 05:36:47 +08:00
|
|
|
/// ANDNP - Bitwise Logical AND NOT of Packed FP values.
|
|
|
|
ANDNP,
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2011-11-19 15:33:10 +08:00
|
|
|
/// PSIGN - Copy integer sign.
|
|
|
|
PSIGN,
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2012-12-05 17:24:57 +08:00
|
|
|
/// BLENDV - Blend where the selector is a register.
|
2011-09-10 04:29:17 +08:00
|
|
|
BLENDV,
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2012-12-05 17:24:57 +08:00
|
|
|
/// BLENDI - Blend where the selector is an immediate.
|
|
|
|
BLENDI,
|
2012-04-11 14:40:27 +08:00
|
|
|
|
2012-12-16 00:47:44 +08:00
|
|
|
// SUBUS - Integer sub with unsigned saturation.
|
|
|
|
SUBUS,
|
|
|
|
|
2011-11-19 17:02:40 +08:00
|
|
|
/// HADD - Integer horizontal add.
|
|
|
|
HADD,
|
|
|
|
|
|
|
|
/// HSUB - Integer horizontal sub.
|
|
|
|
HSUB,
|
|
|
|
|
2011-09-23 04:15:48 +08:00
|
|
|
/// FHADD - Floating point horizontal add.
|
|
|
|
FHADD,
|
|
|
|
|
|
|
|
/// FHSUB - Floating point horizontal sub.
|
|
|
|
FHSUB,
|
|
|
|
|
2012-12-21 22:04:55 +08:00
|
|
|
/// UMAX, UMIN - Unsigned integer max and min.
|
|
|
|
UMAX, UMIN,
|
|
|
|
|
|
|
|
/// SMAX, SMIN - Signed integer max and min.
|
|
|
|
SMAX, SMIN,
|
|
|
|
|
2006-11-11 05:43:37 +08:00
|
|
|
/// FMAX, FMIN - Floating point max and min.
|
|
|
|
///
|
2007-04-21 05:38:10 +08:00
|
|
|
FMAX, FMIN,
|
2007-07-10 08:05:58 +08:00
|
|
|
|
2012-08-19 21:06:16 +08:00
|
|
|
/// FMAXC, FMINC - Commutative FMIN and FMAX.
|
|
|
|
FMAXC, FMINC,
|
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
/// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
|
|
|
|
/// approximation. Note that these typically require refinement
|
|
|
|
/// in order to obtain suitable precision.
|
|
|
|
FRSQRT, FRCP,
|
|
|
|
|
2009-04-09 05:14:34 +08:00
|
|
|
// TLSADDR - Thread Local Storage.
|
|
|
|
TLSADDR,
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2012-06-02 00:27:21 +08:00
|
|
|
// TLSBASEADDR - Thread Local Storage. A call to get the start address
|
|
|
|
// of the TLS block for the current module.
|
|
|
|
TLSBASEADDR,
|
|
|
|
|
2010-06-03 12:07:48 +08:00
|
|
|
// TLSCALL - Thread Local Storage. When calling to an OS provided
|
|
|
|
// thunk at the address from an earlier relocation.
|
|
|
|
TLSCALL,
|
2009-04-09 05:14:34 +08:00
|
|
|
|
2008-05-08 08:57:18 +08:00
|
|
|
// EH_RETURN - Exception Handling helpers.
|
2007-10-12 03:40:01 +08:00
|
|
|
EH_RETURN,
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2012-10-16 06:39:43 +08:00
|
|
|
// EH_SJLJ_SETJMP - SjLj exception handling setjmp.
|
|
|
|
EH_SJLJ_SETJMP,
|
|
|
|
|
|
|
|
// EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
|
|
|
|
EH_SJLJ_LONGJMP,
|
|
|
|
|
2013-02-15 07:17:03 +08:00
|
|
|
/// TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for
|
|
|
|
/// the list of operands.
|
2007-11-16 09:31:51 +08:00
|
|
|
TC_RETURN,
|
|
|
|
|
2008-05-10 05:53:03 +08:00
|
|
|
// VZEXT_MOVL - Vector move low and zero extend.
|
|
|
|
VZEXT_MOVL,
|
|
|
|
|
2012-02-05 11:14:49 +08:00
|
|
|
// VSEXT_MOVL - Vector move low and sign extend.
|
2012-02-02 17:10:43 +08:00
|
|
|
VSEXT_MOVL,
|
|
|
|
|
2012-10-24 01:34:00 +08:00
|
|
|
// VZEXT - Vector integer zero-extend.
|
|
|
|
VZEXT,
|
|
|
|
|
|
|
|
// VSEXT - Vector integer signed-extend.
|
|
|
|
VSEXT,
|
|
|
|
|
2013-08-29 19:56:53 +08:00
|
|
|
// VTRUNC - Vector integer truncate.
|
|
|
|
VTRUNC,
|
|
|
|
|
|
|
|
// VTRUNC - Vector integer truncate with mask.
|
|
|
|
VTRUNCM,
|
|
|
|
|
2012-08-15 05:24:47 +08:00
|
|
|
// VFPEXT - Vector FP extend.
|
|
|
|
VFPEXT,
|
|
|
|
|
2012-10-11 00:53:28 +08:00
|
|
|
// VFPROUND - Vector FP round.
|
|
|
|
VFPROUND,
|
|
|
|
|
2012-01-23 03:15:14 +08:00
|
|
|
// VSHL, VSRL - 128-bit vector logical left / right shift
|
|
|
|
VSHLDQ, VSRLDQ,
|
|
|
|
|
|
|
|
// VSHL, VSRL, VSRA - Vector shift elements
|
|
|
|
VSHL, VSRL, VSRA,
|
|
|
|
|
|
|
|
// VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
|
|
|
|
VSHLI, VSRLI, VSRAI,
|
2009-04-28 02:41:29 +08:00
|
|
|
|
2012-01-23 07:36:02 +08:00
|
|
|
// CMPP - Vector packed double/float comparison.
|
|
|
|
CMPP,
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2008-07-18 00:51:19 +08:00
|
|
|
// PCMP* - Vector integer comparisons.
|
2012-01-23 06:42:16 +08:00
|
|
|
PCMPEQ, PCMPGT,
|
2013-08-21 17:36:02 +08:00
|
|
|
// PCMP*M - Vector integer comparisons, the result is in a mask vector.
|
2013-08-13 21:24:07 +08:00
|
|
|
PCMPEQM, PCMPGTM,
|
|
|
|
|
|
|
|
/// CMPM, CMPMU - Vector comparison generating mask bits for fp and
|
|
|
|
/// integer signed and unsigned data types.
|
|
|
|
CMPM,
|
|
|
|
CMPMU,
|
2008-12-12 08:56:36 +08:00
|
|
|
|
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
llvm-svn: 120935
2010-12-05 15:30:36 +08:00
|
|
|
// ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
|
2010-12-20 08:59:46 +08:00
|
|
|
ADD, SUB, ADC, SBB, SMUL,
|
2009-09-19 03:59:53 +08:00
|
|
|
INC, DEC, OR, XOR, AND,
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2011-10-21 14:55:01 +08:00
|
|
|
BLSI, // BLSI - Extract lowest set isolated bit
|
|
|
|
BLSMSK, // BLSMSK - Get mask up to lowest set bit
|
|
|
|
BLSR, // BLSR - Reset lowest set bit
|
2013-08-30 14:52:21 +08:00
|
|
|
BZHI, // BZHI - Zero high bits
|
2013-09-02 15:53:17 +08:00
|
|
|
BEXTR, // BEXTR - Bit field extract
|
2011-10-21 14:55:01 +08:00
|
|
|
|
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
llvm-svn: 120935
2010-12-05 15:30:36 +08:00
|
|
|
UMUL, // LOW, HI, FLAGS = umul LHS, RHS
|
2009-03-31 05:36:47 +08:00
|
|
|
|
|
|
|
// MUL_IMM - X86 specific multiply by immediate.
|
2009-07-29 08:28:05 +08:00
|
|
|
MUL_IMM,
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2013-08-21 17:36:02 +08:00
|
|
|
// PTEST - Vector bitwise comparisons.
|
2009-08-15 09:38:56 +08:00
|
|
|
PTEST,
|
|
|
|
|
2013-08-21 17:36:02 +08:00
|
|
|
// TESTP - Vector packed fp sign bitwise comparisons.
|
2010-08-11 07:25:42 +08:00
|
|
|
TESTP,
|
|
|
|
|
2013-08-21 17:36:02 +08:00
|
|
|
// TESTM - Vector "test" in AVX-512, the result is in a mask vector.
|
|
|
|
TESTM,
|
|
|
|
|
2013-08-05 16:52:21 +08:00
|
|
|
// OR/AND test for masks
|
|
|
|
KORTEST,
|
|
|
|
KTEST,
|
|
|
|
|
2010-08-21 06:55:05 +08:00
|
|
|
// Several flavors of instructions with vector shuffle behaviors.
|
2013-01-28 14:48:25 +08:00
|
|
|
PALIGNR,
|
2010-08-21 06:55:05 +08:00
|
|
|
PSHUFD,
|
|
|
|
PSHUFHW,
|
|
|
|
PSHUFLW,
|
2012-01-01 07:50:21 +08:00
|
|
|
SHUFP,
|
2010-08-21 06:55:05 +08:00
|
|
|
MOVDDUP,
|
|
|
|
MOVSHDUP,
|
|
|
|
MOVSLDUP,
|
|
|
|
MOVLHPS,
|
|
|
|
MOVLHPD,
|
2010-09-01 05:15:21 +08:00
|
|
|
MOVHLPS,
|
2010-09-01 13:08:25 +08:00
|
|
|
MOVLPS,
|
|
|
|
MOVLPD,
|
2010-08-21 06:55:05 +08:00
|
|
|
MOVSD,
|
|
|
|
MOVSS,
|
2011-12-06 16:21:25 +08:00
|
|
|
UNPCKL,
|
|
|
|
UNPCKH,
|
2011-11-30 14:25:25 +08:00
|
|
|
VPERMILP,
|
2012-04-16 08:41:45 +08:00
|
|
|
VPERMV,
|
2013-08-11 15:55:09 +08:00
|
|
|
VPERMV3,
|
2012-04-16 08:41:45 +08:00
|
|
|
VPERMI,
|
2011-11-30 15:47:51 +08:00
|
|
|
VPERM2X128,
|
2011-08-17 10:29:19 +08:00
|
|
|
VBROADCAST,
|
2013-08-07 20:34:55 +08:00
|
|
|
// masked broadcast
|
|
|
|
VBROADCASTM,
|
2010-08-21 06:55:05 +08:00
|
|
|
|
2012-02-05 11:14:49 +08:00
|
|
|
// PMULUDQ - Vector multiply packed unsigned doubleword integers
|
|
|
|
PMULUDQ,
|
|
|
|
|
2012-08-01 20:06:00 +08:00
|
|
|
// FMA nodes
|
|
|
|
FMADD,
|
|
|
|
FNMADD,
|
|
|
|
FMSUB,
|
|
|
|
FNMSUB,
|
|
|
|
FMADDSUB,
|
|
|
|
FMSUBADD,
|
|
|
|
|
2009-08-15 09:38:56 +08:00
|
|
|
// VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
|
|
|
|
// according to %al. An operator is needed so that this can be expanded
|
|
|
|
// with control flow.
|
2009-09-26 04:36:54 +08:00
|
|
|
VASTART_SAVE_XMM_REGS,
|
|
|
|
|
2010-10-21 09:41:01 +08:00
|
|
|
// WIN_ALLOCA - Windows's _chkstk call to do stack probing.
|
|
|
|
WIN_ALLOCA,
|
2010-03-07 03:32:29 +08:00
|
|
|
|
2011-08-31 03:43:21 +08:00
|
|
|
// SEG_ALLOCA - For allocating variable amounts of stack space when using
|
|
|
|
// segmented stacks. Check if the current stacklet has enough space, and
|
2011-09-07 03:29:31 +08:00
|
|
|
// falls back to heap allocation if not.
|
2011-08-31 03:43:21 +08:00
|
|
|
SEG_ALLOCA,
|
|
|
|
|
2012-02-25 03:01:22 +08:00
|
|
|
// WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
|
|
|
|
WIN_FTOL,
|
|
|
|
|
2010-11-20 19:25:00 +08:00
|
|
|
// Memory barrier
|
|
|
|
MEMBARRIER,
|
|
|
|
MFENCE,
|
|
|
|
SFENCE,
|
|
|
|
LFENCE,
|
|
|
|
|
2012-04-27 20:07:43 +08:00
|
|
|
// FNSTSW16r - Store FP status word into i16 register.
|
|
|
|
FNSTSW16r,
|
|
|
|
|
|
|
|
// SAHF - Store contents of %ah into %eflags.
|
|
|
|
SAHF,
|
|
|
|
|
2012-07-12 17:31:43 +08:00
|
|
|
// RDRAND - Get a random integer and indicate whether it is valid in CF.
|
|
|
|
RDRAND,
|
|
|
|
|
2013-03-29 07:41:26 +08:00
|
|
|
// RDSEED - Get a NIST SP800-90B & C compliant random integer and
|
|
|
|
// indicate whether it is valid in CF.
|
|
|
|
RDSEED,
|
|
|
|
|
2012-08-06 14:22:36 +08:00
|
|
|
// PCMP*STRI
|
|
|
|
PCMPISTRI,
|
|
|
|
PCMPESTRI,
|
|
|
|
|
2013-03-27 06:47:01 +08:00
|
|
|
// XTEST - Test if in transactional execution.
|
|
|
|
XTEST,
|
|
|
|
|
2010-10-21 07:40:27 +08:00
|
|
|
// ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
|
|
|
|
// ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
|
2009-09-26 04:36:54 +08:00
|
|
|
// Atomic 64-bit binary operations.
|
|
|
|
ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
|
|
|
|
ATOMSUB64_DAG,
|
|
|
|
ATOMOR64_DAG,
|
|
|
|
ATOMXOR64_DAG,
|
|
|
|
ATOMAND64_DAG,
|
|
|
|
ATOMNAND64_DAG,
|
2012-09-26 02:08:13 +08:00
|
|
|
ATOMMAX64_DAG,
|
|
|
|
ATOMMIN64_DAG,
|
|
|
|
ATOMUMAX64_DAG,
|
|
|
|
ATOMUMIN64_DAG,
|
2010-07-22 10:48:34 +08:00
|
|
|
ATOMSWAP64_DAG,
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2011-08-27 05:21:21 +08:00
|
|
|
// LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
|
2010-09-22 07:59:42 +08:00
|
|
|
LCMPXCHG_DAG,
|
2010-09-22 08:34:38 +08:00
|
|
|
LCMPXCHG8_DAG,
|
2011-08-27 05:21:21 +08:00
|
|
|
LCMPXCHG16_DAG,
|
2010-03-07 03:32:29 +08:00
|
|
|
|
2010-09-22 08:34:38 +08:00
|
|
|
// VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
|
2010-09-22 09:05:16 +08:00
|
|
|
VZEXT_LOAD,
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2010-09-22 09:11:26 +08:00
|
|
|
// FNSTCW16m - Store FP control world into i16 memory.
|
|
|
|
FNSTCW16m,
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2010-09-22 09:05:16 +08:00
|
|
|
/// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
|
|
|
|
/// integer destination in memory and a FP reg source. This corresponds
|
|
|
|
/// to the X86::FIST*m instructions and the rounding mode change stuff. It
|
|
|
|
/// has two inputs (token chain and address) and two outputs (int value
|
|
|
|
/// and token chain).
|
|
|
|
FP_TO_INT16_IN_MEM,
|
|
|
|
FP_TO_INT32_IN_MEM,
|
2010-09-22 09:28:21 +08:00
|
|
|
FP_TO_INT64_IN_MEM,
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2010-09-22 09:28:21 +08:00
|
|
|
/// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
|
|
|
|
/// integer source in memory and FP reg result. This corresponds to the
|
|
|
|
/// X86::FILD*m instructions. It has three inputs (token chain, address,
|
|
|
|
/// and source type) and two outputs (FP value and token chain). FILD_FLAG
|
|
|
|
/// also produces a flag).
|
|
|
|
FILD,
|
|
|
|
FILD_FLAG,
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2010-09-22 09:28:21 +08:00
|
|
|
/// FLD - This instruction implements an extending load to FP stack slots.
|
|
|
|
/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
|
|
|
|
/// operand, ptr to load from, and a ValueType node indicating the type
|
|
|
|
/// to load to.
|
|
|
|
FLD,
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2010-09-22 09:28:21 +08:00
|
|
|
/// FST - This instruction implements a truncating store to FP stack
|
|
|
|
/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
|
|
|
|
/// chain operand, value to store, address, and a ValueType to store it
|
|
|
|
/// as.
|
2010-10-13 02:00:49 +08:00
|
|
|
FST,
|
|
|
|
|
|
|
|
/// VAARG_64 - This instruction grabs the address of the next argument
|
|
|
|
/// from a va_list. (reads and modifies the va_list in memory)
|
|
|
|
VAARG_64
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2010-03-07 03:32:29 +08:00
|
|
|
// WARNING: Do not add anything in the end unless you want the node to
|
|
|
|
// have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
|
|
|
|
// thought as target memory ops!
|
2005-11-15 08:40:23 +08:00
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2008-01-30 03:34:22 +08:00
|
|
|
/// Define some predicates that are used for node matching.
|
|
|
|
namespace X86 {
|
2013-07-31 19:35:14 +08:00
|
|
|
/// isVEXTRACT128Index - Return true if the specified
|
2011-02-03 23:50:00 +08:00
|
|
|
/// EXTRACT_SUBVECTOR operand specifies a vector extract that is
|
2013-07-31 19:35:14 +08:00
|
|
|
/// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
|
|
|
|
bool isVEXTRACT128Index(SDNode *N);
|
2011-02-03 23:50:00 +08:00
|
|
|
|
2013-07-31 19:35:14 +08:00
|
|
|
/// isVINSERT128Index - Return true if the specified
|
2011-02-05 00:08:29 +08:00
|
|
|
/// INSERT_SUBVECTOR operand specifies a subvector insert that is
|
2013-07-31 19:35:14 +08:00
|
|
|
/// suitable for input to VINSERTF128, VINSERTI128 instructions.
|
|
|
|
bool isVINSERT128Index(SDNode *N);
|
2011-02-05 00:08:29 +08:00
|
|
|
|
2013-07-31 19:35:14 +08:00
|
|
|
/// isVEXTRACT256Index - Return true if the specified
|
|
|
|
/// EXTRACT_SUBVECTOR operand specifies a vector extract that is
|
|
|
|
/// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
|
|
|
|
bool isVEXTRACT256Index(SDNode *N);
|
|
|
|
|
|
|
|
/// isVINSERT256Index - Return true if the specified
|
|
|
|
/// INSERT_SUBVECTOR operand specifies a subvector insert that is
|
|
|
|
/// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
|
|
|
|
bool isVINSERT256Index(SDNode *N);
|
|
|
|
|
|
|
|
/// getExtractVEXTRACT128Immediate - Return the appropriate
|
|
|
|
/// immediate to extract the specified EXTRACT_SUBVECTOR index
|
|
|
|
/// with VEXTRACTF128, VEXTRACTI128 instructions.
|
|
|
|
unsigned getExtractVEXTRACT128Immediate(SDNode *N);
|
|
|
|
|
|
|
|
/// getInsertVINSERT128Immediate - Return the appropriate
|
|
|
|
/// immediate to insert at the specified INSERT_SUBVECTOR index
|
|
|
|
/// with VINSERTF128, VINSERT128 instructions.
|
|
|
|
unsigned getInsertVINSERT128Immediate(SDNode *N);
|
|
|
|
|
|
|
|
/// getExtractVEXTRACT256Immediate - Return the appropriate
|
2011-02-03 23:50:00 +08:00
|
|
|
/// immediate to extract the specified EXTRACT_SUBVECTOR index
|
2013-07-31 19:35:14 +08:00
|
|
|
/// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
|
|
|
|
unsigned getExtractVEXTRACT256Immediate(SDNode *N);
|
2011-02-03 23:50:00 +08:00
|
|
|
|
2013-07-31 19:35:14 +08:00
|
|
|
/// getInsertVINSERT256Immediate - Return the appropriate
|
2011-02-05 00:08:29 +08:00
|
|
|
/// immediate to insert at the specified INSERT_SUBVECTOR index
|
2013-07-31 19:35:14 +08:00
|
|
|
/// with VINSERTF64x4, VINSERTI64x4 instructions.
|
|
|
|
unsigned getInsertVINSERT256Immediate(SDNode *N);
|
2011-02-05 00:08:29 +08:00
|
|
|
|
2009-07-30 16:33:02 +08:00
|
|
|
/// isZeroNode - Returns true if Elt is a constant zero or a floating point
|
|
|
|
/// constant +0.0.
|
|
|
|
bool isZeroNode(SDValue Elt);
|
2009-08-06 07:01:26 +08:00
|
|
|
|
|
|
|
/// isOffsetSuitableForCodeModel - Returns true of the given offset can be
|
|
|
|
/// fit into displacement field of the instruction.
|
|
|
|
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
|
|
|
|
bool hasSymbolicDisplacement = true);
|
2011-06-24 01:54:54 +08:00
|
|
|
|
|
|
|
|
|
|
|
/// isCalleePop - Determines whether the callee is required to pop its
|
|
|
|
/// own arguments. Callee pop is necessary to support tail calls.
|
|
|
|
bool isCalleePop(CallingConv::ID CallingConv,
|
|
|
|
bool is64Bit, bool IsVarArg, bool TailCallOpt);
|
2008-01-30 03:34:22 +08:00
|
|
|
}
|
|
|
|
|
2006-10-19 02:26:48 +08:00
|
|
|
//===--------------------------------------------------------------------===//
|
2005-11-15 08:40:23 +08:00
|
|
|
// X86TargetLowering - X86 Implementation of the TargetLowering interface
|
|
|
|
class X86TargetLowering : public TargetLowering {
|
|
|
|
public:
|
2008-05-14 09:58:56 +08:00
|
|
|
explicit X86TargetLowering(X86TargetMachine &TM);
|
2005-11-15 08:40:23 +08:00
|
|
|
|
2010-01-26 13:02:42 +08:00
|
|
|
virtual unsigned getJumpTableEncoding() const;
|
2010-01-26 07:38:14 +08:00
|
|
|
|
2013-03-02 02:40:30 +08:00
|
|
|
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2010-01-26 13:02:42 +08:00
|
|
|
virtual const MCExpr *
|
|
|
|
LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
|
|
|
|
const MachineBasicBlock *MBB, unsigned uid,
|
|
|
|
MCContext &Ctx) const;
|
2010-10-21 07:40:27 +08:00
|
|
|
|
Much improved pic jumptable codegen:
Then:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
imull $4, %ecx, %ecx
leal LJTI1_0-"L1$pb"(%eax), %edx
addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx
jmpl *%edx
.align 2
.set L1_0_set_3,LBB1_3-LJTI1_0
.set L1_0_set_2,LBB1_2-LJTI1_0
.set L1_0_set_5,LBB1_5-LJTI1_0
.set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
Now:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
jmpl *%eax
.align 2
.set L1_0_set_3,LBB1_3-"L1$pb"
.set L1_0_set_2,LBB1_2-"L1$pb"
.set L1_0_set_5,LBB1_5-"L1$pb"
.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
llvm-svn: 43924
2007-11-09 09:32:10 +08:00
|
|
|
/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
|
|
|
|
/// jumptable.
|
2010-01-26 13:02:42 +08:00
|
|
|
virtual SDValue getPICJumpTableRelocBase(SDValue Table,
|
|
|
|
SelectionDAG &DAG) const;
|
2010-01-26 14:28:43 +08:00
|
|
|
virtual const MCExpr *
|
|
|
|
getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
|
|
|
|
unsigned JTI, MCContext &Ctx) const;
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2008-01-24 07:17:41 +08:00
|
|
|
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
|
|
|
|
/// function arguments in the caller parameter area. For X86, aggregates
|
|
|
|
/// that contains are placed at 16-byte boundaries while the rest are at
|
|
|
|
/// 4-byte boundaries.
|
2011-07-18 12:54:35 +08:00
|
|
|
virtual unsigned getByValTypeAlignment(Type *Ty) const;
|
2008-05-15 16:39:06 +08:00
|
|
|
|
|
|
|
/// getOptimalMemOpType - Returns the target specific optimal type for load
|
2010-04-03 03:36:14 +08:00
|
|
|
/// and store operations as a result of memset, memcpy, and memmove
|
|
|
|
/// lowering. If DstAlign is zero that means it's safe to destination
|
|
|
|
/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
|
|
|
|
/// means there isn't a need to check it against alignment requirement,
|
2012-12-12 10:34:41 +08:00
|
|
|
/// probably because the source does not need to be loaded. If 'IsMemset' is
|
|
|
|
/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
|
|
|
|
/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
|
|
|
|
/// source is constant so it does not need to be loaded.
|
2010-04-17 04:11:05 +08:00
|
|
|
/// It returns EVT::Other if the type should be determined using generic
|
|
|
|
/// target-independent logic.
|
2010-04-03 03:36:14 +08:00
|
|
|
virtual EVT
|
2013-05-18 08:21:46 +08:00
|
|
|
getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
|
2012-12-12 10:34:41 +08:00
|
|
|
bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
|
2010-04-17 04:11:05 +08:00
|
|
|
MachineFunction &MF) const;
|
2009-08-16 05:21:19 +08:00
|
|
|
|
2012-12-12 09:32:07 +08:00
|
|
|
/// isSafeMemOpType - Returns true if it's safe to use load / store of the
|
2012-12-12 08:42:09 +08:00
|
|
|
/// specified type to expand memcpy / memset inline. This is mostly true
|
2012-12-12 09:32:07 +08:00
|
|
|
/// for all types except for some special cases. For example, on X86
|
2012-12-12 08:42:09 +08:00
|
|
|
/// targets without SSE2 f64 load / store are done with fldl / fstpl which
|
2012-12-12 09:32:07 +08:00
|
|
|
/// also does type conversion. Note the specified type doesn't have to be
|
|
|
|
/// legal as the hook is used before type legalization.
|
|
|
|
virtual bool isSafeMemOpType(MVT VT) const;
|
2012-12-12 08:42:09 +08:00
|
|
|
|
2009-08-16 05:21:19 +08:00
|
|
|
/// allowsUnalignedMemoryAccesses - Returns true if the target allows
|
2012-12-11 07:21:26 +08:00
|
|
|
/// unaligned memory accesses. of the specified type. Returns whether it
|
|
|
|
/// is "fast" by reference in the second argument.
|
|
|
|
virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
|
2009-07-01 06:38:32 +08:00
|
|
|
|
2005-11-15 08:40:23 +08:00
|
|
|
/// LowerOperation - Provide custom lowering hooks for some operations.
|
|
|
|
///
|
2010-04-17 23:26:15 +08:00
|
|
|
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
|
2005-11-15 08:40:23 +08:00
|
|
|
|
2008-12-01 19:39:25 +08:00
|
|
|
/// ReplaceNodeResults - Replace the results of node with an illegal result
|
|
|
|
/// type with new values built out of custom code.
|
2007-11-24 15:07:01 +08:00
|
|
|
///
|
2008-12-01 19:39:25 +08:00
|
|
|
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
|
2010-04-17 23:26:15 +08:00
|
|
|
SelectionDAG &DAG) const;
|
2007-11-24 15:07:01 +08:00
|
|
|
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
X86 target specific DAG combine: turn build_vector (load x), (load x+4),
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).
e.g.
__m128 test(float a, float b, float c, float d) {
return _mm_set_ps(d, c, b, a);
}
_test:
movups 4(%esp), %xmm0
ret
llvm-svn: 29042
2006-07-07 16:33:52 +08:00
|
|
|
|
2010-04-17 14:13:15 +08:00
|
|
|
/// isTypeDesirableForOp - Return true if the target has native support for
|
|
|
|
/// the specified value type and it is 'desirable' to use the type for the
|
|
|
|
/// given node type. e.g. On x86 i16 is legal, but undesirable since i16
|
|
|
|
/// instruction encodings are longer and some i16 instructions are slow.
|
|
|
|
virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
|
|
|
|
|
|
|
|
/// isTypeDesirable - Return true if the target has native support for the
|
|
|
|
/// specified value type and it is 'desirable' to use the type. e.g. On x86
|
|
|
|
/// i16 is legal, but undesirable since i16 instruction encodings are longer
|
|
|
|
/// and some i16 instructions are slow.
|
|
|
|
virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
|
2010-04-16 14:14:10 +08:00
|
|
|
|
2010-05-01 08:01:06 +08:00
|
|
|
virtual MachineBasicBlock *
|
|
|
|
EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB) const;
|
2006-01-11 08:33:36 +08:00
|
|
|
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2005-12-20 14:22:03 +08:00
|
|
|
/// getTargetNodeName - This method returns the name of a target specific
|
|
|
|
/// DAG node.
|
|
|
|
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
|
|
|
|
2011-09-07 03:07:46 +08:00
|
|
|
/// getSetCCResultType - Return the value type to use for ISD::SETCC.
|
2013-05-18 08:21:46 +08:00
|
|
|
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
|
2008-03-10 23:42:14 +08:00
|
|
|
|
2010-10-21 07:40:27 +08:00
|
|
|
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
|
|
|
|
/// in Mask are known to be either zero or one and return them in the
|
2006-02-17 05:11:51 +08:00
|
|
|
/// KnownZero/KnownOne bitsets.
|
2008-07-28 05:46:04 +08:00
|
|
|
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
|
2010-10-21 07:40:27 +08:00
|
|
|
APInt &KnownZero,
|
2008-02-13 08:35:47 +08:00
|
|
|
APInt &KnownOne,
|
2007-06-22 22:59:07 +08:00
|
|
|
const SelectionDAG &DAG,
|
2006-02-17 05:11:51 +08:00
|
|
|
unsigned Depth = 0) const;
|
2008-05-13 03:56:52 +08:00
|
|
|
|
2010-09-22 04:42:50 +08:00
|
|
|
// ComputeNumSignBitsForTargetNode - Determine the number of bits in the
|
|
|
|
// operation that are sign bits.
|
|
|
|
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
|
|
|
|
unsigned Depth) const;
|
|
|
|
|
2008-05-13 03:56:52 +08:00
|
|
|
virtual bool
|
2010-04-15 09:51:59 +08:00
|
|
|
isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2010-04-17 23:26:15 +08:00
|
|
|
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
|
2005-11-15 08:40:23 +08:00
|
|
|
|
2009-07-21 01:51:36 +08:00
|
|
|
virtual bool ExpandInlineAsm(CallInst *CI) const;
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2007-03-25 10:14:49 +08:00
|
|
|
ConstraintType getConstraintType(const std::string &Constraint) const;
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2010-10-30 01:29:13 +08:00
|
|
|
/// Examine constraint string and operand type and determine a weight value.
|
2010-09-14 02:15:37 +08:00
|
|
|
/// The operand object must already have been set up with the operand type.
|
2010-10-30 01:29:13 +08:00
|
|
|
virtual ConstraintWeight getSingleConstraintMatchWeight(
|
2010-09-14 02:15:37 +08:00
|
|
|
AsmOperandInfo &info, const char *constraint) const;
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2009-08-11 06:56:29 +08:00
|
|
|
virtual const char *LowerXConstraint(EVT ConstraintVT) const;
|
2008-01-29 10:21:21 +08:00
|
|
|
|
2007-08-25 08:47:38 +08:00
|
|
|
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
2008-09-24 08:05:32 +08:00
|
|
|
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
|
|
|
|
/// true it means one of the asm constraint of the inline asm instruction
|
|
|
|
/// being processed is 'm'.
|
2008-07-28 05:46:04 +08:00
|
|
|
virtual void LowerAsmOperandForConstraint(SDValue Op,
|
2011-06-03 07:16:42 +08:00
|
|
|
std::string &Constraint,
|
2008-07-28 05:46:04 +08:00
|
|
|
std::vector<SDValue> &Ops,
|
2008-04-27 07:02:14 +08:00
|
|
|
SelectionDAG &DAG) const;
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2006-10-19 02:26:48 +08:00
|
|
|
/// getRegForInlineAsmConstraint - Given a physical register constraint
|
|
|
|
/// (e.g. {edx}), return the register number and the register class for the
|
|
|
|
/// register. This should only be used for C_Register constraints. On
|
|
|
|
/// error, this returns a register number of 0.
|
2010-10-21 07:40:27 +08:00
|
|
|
std::pair<unsigned, const TargetRegisterClass*>
|
2006-08-01 07:26:50 +08:00
|
|
|
getRegForInlineAsmConstraint(const std::string &Constraint,
|
2013-06-23 02:37:38 +08:00
|
|
|
MVT VT) const;
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2007-03-31 07:15:24 +08:00
|
|
|
/// isLegalAddressingMode - Return true if the addressing mode represented
|
|
|
|
/// by AM is legal for this target, for a load/store of the specified type.
|
2011-07-18 12:54:35 +08:00
|
|
|
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
|
2007-03-31 07:15:24 +08:00
|
|
|
|
2012-07-17 14:53:39 +08:00
|
|
|
/// isLegalICmpImmediate - Return true if the specified immediate is legal
|
|
|
|
/// icmp immediate, that is the target has icmp instructions which can
|
|
|
|
/// compare a register against the immediate without having to materialize
|
|
|
|
/// the immediate into a register.
|
|
|
|
virtual bool isLegalICmpImmediate(int64_t Imm) const;
|
|
|
|
|
|
|
|
/// isLegalAddImmediate - Return true if the specified immediate is legal
|
|
|
|
/// add immediate, that is the target has add instructions which can
|
|
|
|
/// add a register and the immediate without having to materialize
|
|
|
|
/// the immediate into a register.
|
|
|
|
virtual bool isLegalAddImmediate(int64_t Imm) const;
|
|
|
|
|
Loosen up iv reuse to allow reuse of the same stride but a larger type when truncating from the larger type to smaller type is free.
e.g.
Turns this loop:
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
movw %dx, %si
LBB1_2: # bb
movl L_X$non_lazy_ptr, %edi
movw %si, (%edi)
movl L_Y$non_lazy_ptr, %edi
movw %dx, (%edi)
addw $4, %dx
incw %si
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
into
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
LBB1_2: # bb
movl L_X$non_lazy_ptr, %esi
movw %cx, (%esi)
movl L_Y$non_lazy_ptr, %esi
movw %dx, (%esi)
addw $4, %dx
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
llvm-svn: 43375
2007-10-26 09:56:11 +08:00
|
|
|
/// isTruncateFree - Return true if it's free to truncate a value of
|
|
|
|
/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
|
|
|
|
/// register EAX to i16 by referencing its sub-register AX.
|
2011-07-18 12:54:35 +08:00
|
|
|
virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
|
2009-08-11 06:56:29 +08:00
|
|
|
virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
|
Refactor isInTailCallPosition handling
This change came about primarily because of two issues in the existing code.
Niether of:
define i64 @test1(i64 %val) {
%in = trunc i64 %val to i32
tail call i32 @ret32(i32 returned %in)
ret i64 %val
}
define i64 @test2(i64 %val) {
tail call i32 @ret32(i32 returned undef)
ret i32 42
}
should be tail calls, and the function sameNoopInput is responsible. The main
problem is that it is completely symmetric in the "tail call" and "ret" value,
but in reality different things are allowed on each side.
For these cases:
1. Any truncation should lead to a larger value being generated by "tail call"
than needed by "ret".
2. Undef should only be allowed as a source for ret, not as a result of the
call.
Along the way I noticed that a mismatch between what this function treats as a
valid truncation and what the backends see can lead to invalid calls as well
(see x86-32 test case).
This patch refactors the code so that instead of being based primarily on
values which it recurses into when necessary, it starts by inspecting the type
and considers each fundamental slot that the backend will see in turn. For
example, given a pathological function that returned {{}, {{}, i32, {}}, i32}
we would consider each "real" i32 in turn, and ask if it passes through
unchanged. This is much closer to what the backend sees as a result of
ComputeValueVTs.
Aside from the bug fixes, this eliminates the recursion that's going on and, I
believe, makes the bulk of the code significantly easier to understand. The
trade-off is the nasty iterators needed to find the real types inside a
returned value.
llvm-svn: 187787
2013-08-06 17:12:35 +08:00
|
|
|
virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
|
|
|
|
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
/// isZExtFree - Return true if any actual instruction that defines a
|
|
|
|
/// value of type Ty1 implicit zero-extends the value to Ty2 in the result
|
|
|
|
/// register. This does not necessarily include registers defined in
|
|
|
|
/// unknown ways, such as incoming arguments, or copies from unknown
|
|
|
|
/// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
|
|
|
|
/// does not necessarily apply to truncate instructions. e.g. on x86-64,
|
|
|
|
/// all instructions that define 32-bit values implicit zero-extend the
|
|
|
|
/// result out to 64 bits.
|
2011-07-18 12:54:35 +08:00
|
|
|
virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
|
2009-08-11 06:56:29 +08:00
|
|
|
virtual bool isZExtFree(EVT VT1, EVT VT2) const;
|
2012-12-07 03:13:27 +08:00
|
|
|
virtual bool isZExtFree(SDValue Val, EVT VT2) const;
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
|
|
|
|
/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
|
|
|
|
/// expanded to FMAs when this method returns true, otherwise fmuladd is
|
|
|
|
/// expanded to fmul + fadd.
|
|
|
|
virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
|
2012-08-01 20:06:00 +08:00
|
|
|
|
2009-05-28 08:35:15 +08:00
|
|
|
/// isNarrowingProfitable - Return true if it's profitable to narrow
|
|
|
|
/// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
|
|
|
|
/// from i32 to i8 but not from i32 to i16.
|
2009-08-11 06:56:29 +08:00
|
|
|
virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
|
2009-05-28 08:35:15 +08:00
|
|
|
|
2009-10-28 03:56:55 +08:00
|
|
|
/// isFPImmLegal - Returns true if the target can instruction select the
|
|
|
|
/// specified FP immediate natively. If false, the legalizer will
|
|
|
|
/// materialize the FP immediate as a load from a constant pool.
|
2009-10-28 09:43:28 +08:00
|
|
|
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
2009-10-28 03:56:55 +08:00
|
|
|
|
2006-03-23 02:59:22 +08:00
|
|
|
/// isShuffleMaskLegal - Targets can use this to indicate that they only
|
|
|
|
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
|
2006-10-19 02:26:48 +08:00
|
|
|
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
|
|
|
|
/// values are assumed to be legal.
|
2009-04-29 13:20:52 +08:00
|
|
|
virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT) const;
|
2006-04-20 16:58:49 +08:00
|
|
|
|
|
|
|
/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
|
|
|
|
/// used by Targets can use this to indicate if there is a suitable
|
|
|
|
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
|
|
|
|
/// pool entry.
|
2009-04-29 13:20:52 +08:00
|
|
|
virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT) const;
|
2008-03-05 09:30:59 +08:00
|
|
|
|
|
|
|
/// ShouldShrinkFPConstant - If true, then instruction selection should
|
|
|
|
/// seek to shrink the FP constant of the specified type to a smaller type
|
|
|
|
/// in order to save space and / or reduce runtime.
|
2009-08-11 06:56:29 +08:00
|
|
|
virtual bool ShouldShrinkFPConstant(EVT VT) const {
|
2008-03-05 09:30:59 +08:00
|
|
|
// Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
|
|
|
|
// expensive than a straight movsd. On the other hand, it's important to
|
|
|
|
// shrink long double fp constant since fldt is very slow.
|
2009-08-12 04:47:22 +08:00
|
|
|
return !X86ScalarSSEf64 || VT == MVT::f80;
|
2008-03-05 09:30:59 +08:00
|
|
|
}
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2010-05-12 00:21:03 +08:00
|
|
|
const X86Subtarget* getSubtarget() const {
|
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
llvm-svn: 49572
2008-04-12 12:36:06 +08:00
|
|
|
return Subtarget;
|
2007-11-06 07:12:20 +08:00
|
|
|
}
|
|
|
|
|
2008-01-18 14:52:41 +08:00
|
|
|
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
|
|
|
|
/// computed in an SSE register, not on the X87 floating point stack.
|
2009-08-11 06:56:29 +08:00
|
|
|
bool isScalarFPTypeInSSEReg(EVT VT) const {
|
2009-08-12 04:47:22 +08:00
|
|
|
return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
|
|
|
|
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
|
2008-01-18 14:52:41 +08:00
|
|
|
}
|
2008-08-20 05:32:53 +08:00
|
|
|
|
2012-02-25 03:01:22 +08:00
|
|
|
/// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
|
|
|
|
/// for fptoui.
|
|
|
|
bool isTargetFTOL() const {
|
|
|
|
return Subtarget->isTargetWindows() && !Subtarget->is64Bit();
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
|
|
|
|
/// used for fptoui to the given type.
|
|
|
|
bool isIntegerTypeFTOL(EVT VT) const {
|
|
|
|
return isTargetFTOL() && VT == MVT::i64;
|
|
|
|
}
|
|
|
|
|
2008-08-20 05:32:53 +08:00
|
|
|
/// createFastISel - This method returns a target specific FastISel object,
|
|
|
|
/// or null if the target does not support "fast" ISel.
|
2012-08-03 12:06:28 +08:00
|
|
|
virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
|
|
const TargetLibraryInfo *libInfo) const;
|
2009-07-01 06:38:32 +08:00
|
|
|
|
2010-07-06 13:18:56 +08:00
|
|
|
/// getStackCookieLocation - Return true if the target stores stack
|
|
|
|
/// protector cookies at a fixed offset in some non-standard address
|
|
|
|
/// space, and populates the address space and offset as
|
|
|
|
/// appropriate.
|
|
|
|
virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
|
|
|
|
|
2011-06-07 07:15:58 +08:00
|
|
|
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
|
|
|
|
SelectionDAG &DAG) const;
|
|
|
|
|
2013-04-06 05:52:40 +08:00
|
|
|
/// \brief Reset the operation actions based on target options.
|
|
|
|
virtual void resetOperationActions();
|
|
|
|
|
2010-07-27 05:50:05 +08:00
|
|
|
protected:
|
|
|
|
std::pair<const TargetRegisterClass*, uint8_t>
|
2012-12-19 19:30:36 +08:00
|
|
|
findRepresentativeClass(MVT VT) const;
|
2010-07-27 05:50:05 +08:00
|
|
|
|
2005-11-15 08:40:23 +08:00
|
|
|
private:
|
2006-04-26 04:13:52 +08:00
|
|
|
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
|
|
|
|
/// make the right decision when generating code for different targets.
|
|
|
|
const X86Subtarget *Subtarget;
|
2012-10-09 00:38:25 +08:00
|
|
|
const DataLayout *TD;
|
2006-04-26 04:13:52 +08:00
|
|
|
|
2013-04-06 05:52:40 +08:00
|
|
|
/// Used to store the TargetOptions so that we don't waste time resetting
|
|
|
|
/// the operation actions unless we have to.
|
|
|
|
TargetOptions TO;
|
|
|
|
|
2010-10-21 07:40:27 +08:00
|
|
|
/// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
|
2007-09-23 22:52:20 +08:00
|
|
|
/// floating point ops.
|
|
|
|
/// When SSE is available, use it for f32 operations.
|
|
|
|
/// When SSE2 is available, use it for f64 operations.
|
|
|
|
bool X86ScalarSSEf32;
|
|
|
|
bool X86ScalarSSEf64;
|
2008-01-30 03:34:22 +08:00
|
|
|
|
2009-10-28 03:56:55 +08:00
|
|
|
/// LegalFPImmediates - A list of legal fp immediates.
|
|
|
|
std::vector<APFloat> LegalFPImmediates;
|
|
|
|
|
|
|
|
/// addLegalFPImmediate - Indicate that this x86 target can instruction
|
|
|
|
/// select the specified FP immediate natively.
|
|
|
|
void addLegalFPImmediate(const APFloat& Imm) {
|
|
|
|
LegalFPImmediates.push_back(Imm);
|
|
|
|
}
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
|
2009-09-02 16:44:58 +08:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
2013-05-25 10:42:55 +08:00
|
|
|
SDLoc dl, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue LowerMemArgument(SDValue Chain,
|
2009-09-02 16:44:58 +08:00
|
|
|
CallingConv::ID CallConv,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &ArgInfo,
|
2013-05-25 10:42:55 +08:00
|
|
|
SDLoc dl, SelectionDAG &DAG,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const CCValAssign &VA, MachineFrameInfo *MFI,
|
2010-04-17 23:26:15 +08:00
|
|
|
unsigned i) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
|
2013-05-25 10:42:55 +08:00
|
|
|
SDLoc dl, SelectionDAG &DAG,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const CCValAssign &VA,
|
2010-04-17 23:26:15 +08:00
|
|
|
ISD::ArgFlagsTy Flags) const;
|
2007-08-31 23:06:30 +08:00
|
|
|
|
2008-01-06 00:56:59 +08:00
|
|
|
// Call lowering helpers.
|
2010-01-27 08:07:07 +08:00
|
|
|
|
|
|
|
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
|
|
|
|
/// for tail call optimization. Targets which want to do tail call
|
|
|
|
/// optimization should implement this function.
|
2010-02-03 07:55:14 +08:00
|
|
|
bool IsEligibleForTailCallOptimization(SDValue Callee,
|
2010-01-27 08:07:07 +08:00
|
|
|
CallingConv::ID CalleeCC,
|
|
|
|
bool isVarArg,
|
2010-03-16 02:54:48 +08:00
|
|
|
bool isCalleeStructRet,
|
|
|
|
bool isCallerStructRet,
|
2012-09-25 13:32:34 +08:00
|
|
|
Type *RetTy,
|
2010-01-27 14:25:16 +08:00
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
2010-07-07 23:54:55 +08:00
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
2010-01-27 14:25:16 +08:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
2010-01-27 08:07:07 +08:00
|
|
|
SelectionDAG& DAG) const;
|
2010-04-17 23:26:15 +08:00
|
|
|
bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
|
|
|
|
SDValue Chain, bool IsTailCall, bool Is64Bit,
|
2013-05-25 10:42:55 +08:00
|
|
|
int FPDiff, SDLoc dl) const;
|
2008-04-13 02:11:06 +08:00
|
|
|
|
2010-04-17 23:26:15 +08:00
|
|
|
unsigned GetAlignedArgumentStackSize(unsigned StackSize,
|
|
|
|
SelectionDAG &DAG) const;
|
2006-01-27 16:10:46 +08:00
|
|
|
|
2009-05-23 17:59:16 +08:00
|
|
|
std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
|
2012-02-25 11:37:25 +08:00
|
|
|
bool isSigned,
|
|
|
|
bool isReplace) const;
|
Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g.
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>
iff ptr is 16-byte aligned (or can be made into 16-byte aligned).
llvm-svn: 90984
2009-12-10 05:00:30 +08:00
|
|
|
|
2010-04-17 23:26:15 +08:00
|
|
|
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
2013-08-05 16:52:21 +08:00
|
|
|
SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
|
2010-04-17 23:26:15 +08:00
|
|
|
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
2013-05-25 10:42:55 +08:00
|
|
|
SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
|
2009-02-05 04:06:27 +08:00
|
|
|
int64_t Offset, SelectionDAG &DAG) const;
|
2010-04-17 23:26:15 +08:00
|
|
|
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
|
2011-05-11 16:12:09 +08:00
|
|
|
SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
|
2010-04-17 23:26:15 +08:00
|
|
|
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
|
2012-10-24 01:36:08 +08:00
|
|
|
SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
|
2013-01-21 05:34:37 +08:00
|
|
|
SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
|
2010-04-17 23:26:15 +08:00
|
|
|
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
|
2010-04-21 09:47:12 +08:00
|
|
|
SDValue LowerToBT(SDValue And, ISD::CondCode CC,
|
2013-05-25 10:42:55 +08:00
|
|
|
SDLoc dl, SelectionDAG &DAG) const;
|
2010-04-17 23:26:15 +08:00
|
|
|
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
|
2012-10-16 06:39:43 +08:00
|
|
|
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
|
2011-09-06 21:37:06 +08:00
|
|
|
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
2010-04-17 23:26:15 +08:00
|
|
|
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
|
2011-07-14 19:11:14 +08:00
|
|
|
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
|
2008-12-01 19:39:25 +08:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
virtual SDValue
|
|
|
|
LowerFormalArguments(SDValue Chain,
|
2009-09-02 16:44:58 +08:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
2013-05-25 10:42:55 +08:00
|
|
|
SDLoc dl, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
virtual SDValue
|
2012-05-26 00:35:28 +08:00
|
|
|
LowerCall(CallLoweringInfo &CLI,
|
2010-04-17 23:26:15 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
|
|
|
virtual SDValue
|
|
|
|
LowerReturn(SDValue Chain,
|
2009-09-02 16:44:58 +08:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
2010-07-07 23:54:55 +08:00
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
2013-05-25 10:42:55 +08:00
|
|
|
SDLoc dl, SelectionDAG &DAG) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
2012-04-10 09:51:00 +08:00
|
|
|
virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
|
2010-12-01 07:55:39 +08:00
|
|
|
|
2011-03-21 09:19:09 +08:00
|
|
|
virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
|
|
|
|
|
2012-12-19 20:02:25 +08:00
|
|
|
virtual MVT
|
|
|
|
getTypeForExtArgOrReturn(MVT VT, ISD::NodeType ExtendKind) const;
|
2011-03-17 06:20:18 +08:00
|
|
|
|
2009-11-07 10:11:54 +08:00
|
|
|
virtual bool
|
2011-06-09 07:55:35 +08:00
|
|
|
CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
|
2012-07-19 08:15:11 +08:00
|
|
|
bool isVarArg,
|
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
|
|
LLVMContext &Context) const;
|
2009-11-07 10:11:54 +08:00
|
|
|
|
2012-09-20 11:06:15 +08:00
|
|
|
/// Utility function to emit atomic-load-arith operations (and, or, xor,
|
|
|
|
/// nand, max, min, umax, umin). It takes the corresponding instruction to
|
|
|
|
/// expand, the associated machine basic block, and the associated X86
|
|
|
|
/// opcodes for reg/reg.
|
|
|
|
MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
|
|
|
|
/// Utility function to emit atomic-load-arith operations (and, or, xor,
|
|
|
|
/// nand, add, sub, swap) for 64-bit operands on 32-bit target.
|
|
|
|
MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB) const;
|
2009-03-05 03:44:21 +08:00
|
|
|
|
2010-10-13 02:00:49 +08:00
|
|
|
// Utility function to emit the low-level va_arg code for X86-64.
|
|
|
|
MachineBasicBlock *EmitVAARG64WithCustomInserter(
|
|
|
|
MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
|
2009-08-15 09:38:56 +08:00
|
|
|
/// Utility function to emit the xmm reg save portion of va_start.
|
|
|
|
MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
|
|
|
|
MachineInstr *BInstr,
|
|
|
|
MachineBasicBlock *BB) const;
|
|
|
|
|
2009-09-02 13:57:00 +08:00
|
|
|
MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
|
2010-05-01 08:01:06 +08:00
|
|
|
MachineBasicBlock *BB) const;
|
2010-03-07 03:32:29 +08:00
|
|
|
|
2010-10-21 09:41:01 +08:00
|
|
|
MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
|
2010-05-01 08:01:06 +08:00
|
|
|
MachineBasicBlock *BB) const;
|
2010-10-21 07:40:27 +08:00
|
|
|
|
2011-08-31 03:47:04 +08:00
|
|
|
MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *BB,
|
|
|
|
bool Is64Bit) const;
|
|
|
|
|
2010-06-03 12:07:48 +08:00
|
|
|
MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *BB) const;
|
2010-03-07 03:32:29 +08:00
|
|
|
|
2010-11-28 04:43:02 +08:00
|
|
|
MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *BB) const;
|
|
|
|
|
2012-10-16 06:39:43 +08:00
|
|
|
MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
|
|
|
|
MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
|
2009-03-05 03:44:21 +08:00
|
|
|
/// Emit nodes that will be selected as "test Op0,Op0", or something
|
2009-03-07 09:58:32 +08:00
|
|
|
/// equivalent, for use with the given x86 condition code.
|
2010-04-27 03:06:11 +08:00
|
|
|
SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
|
2009-03-05 03:44:21 +08:00
|
|
|
|
|
|
|
/// Emit nodes that will be selected as "cmp Op0,Op1", or something
|
2009-03-07 09:58:32 +08:00
|
|
|
/// equivalent, for use with the given x86 condition code.
|
2010-04-27 03:06:11 +08:00
|
|
|
SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
|
2010-04-17 23:26:15 +08:00
|
|
|
SelectionDAG &DAG) const;
|
2012-04-27 20:07:43 +08:00
|
|
|
|
|
|
|
/// Convert a comparison if required by the subtarget.
|
|
|
|
SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
|
2005-11-15 08:40:23 +08:00
|
|
|
};
|
2008-09-03 08:03:49 +08:00
|
|
|
|
|
|
|
namespace X86 {
|
2012-08-03 12:06:28 +08:00
|
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
|
|
const TargetLibraryInfo *libInfo);
|
2008-09-03 08:03:49 +08:00
|
|
|
}
|
2005-11-15 08:40:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif // X86ISELLOWERING_H
|