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llvm-project/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A5...

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[ARM64] Increases the Sched Model accuracy for Cortex-A53. Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D3769 llvm-svn: 209001
2014-05-17 01:15:33 +08:00
; REQUIRES: asserts
CodeGen: Rename DEBUG_TYPE to match passnames Rename the DEBUG_TYPE to match the names of corresponding passes where it makes sense. Also establish the pattern of simply referencing DEBUG_TYPE instead of repeating the passname where possible. llvm-svn: 303921
2017-05-26 05:26:32 +08:00
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
[ARM64] Increases the Sched Model accuracy for Cortex-A53. Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D3769 llvm-svn: 209001
2014-05-17 01:15:33 +08:00
;
; For Cortex-A53, shiftable operands that are not actually shifted
; are not needed for an additional two cycles.
;
; CHECK: ********** MI Scheduling **********
; CHECK: shiftable
[CodeGen] Print RegClasses on MI in verbose mode r322086 removed the trailing information describing reg classes for each register. This patch adds printing reg classes next to every register when individual operands/instructions/basic blocks are printed. In the case of dumping MIR or printing a full function, by default don't print it. Differential Revision: https://reviews.llvm.org/D42239 llvm-svn: 322867
2018-01-19 01:59:06 +08:00
; CHECK: SU(2): %2:gpr64common = SUBXri %1:gpr64common, 20, 0
[AArch64] Fix the ordering of the accumulate operand in SchedRW list. Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D4037 llvm-svn: 210446
2014-06-09 09:54:00 +08:00
; CHECK: Successors:
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
2017-11-30 20:12:19 +08:00
; CHECK-NEXT: SU(4): Data Latency=1 Reg=%2
; CHECK-NEXT: SU(3): Data Latency=2 Reg=%2
[ARM64] Increases the Sched Model accuracy for Cortex-A53. Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D3769 llvm-svn: 209001
2014-05-17 01:15:33 +08:00
; CHECK: ********** INTERVALS **********
define i64 @shiftable(i64 %A, i64 %B) {
%tmp0 = sub i64 %B, 20
%tmp1 = shl i64 %tmp0, 5;
%tmp2 = add i64 %A, %tmp1;
%tmp3 = add i64 %A, %tmp0
%tmp4 = mul i64 %tmp2, %tmp3
ret i64 %tmp4
}