llvm-project/llvm/test/CodeGen/AArch64/arm64-frame-index.ll

; RUN: llc < %s -mtriple=arm64-apple-ios -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
; rdar://11935841

define void @t1() nounwind ssp {
entry:
; CHECK-LABEL: t1:
; CHECK-NOT: add x{{[0-9]+}}, sp
; CHECK: stp x28, x27, [sp, #-16]!
  %v = alloca [288 x i32], align 4
  unreachable
}
[AArch64] Register passes so they can be run by llc Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322 2016-08-01 13:56:57 +08:00			`; RUN: llc < %s -mtriple=arm64-apple-ios -aarch64-enable-atomic-cfg-tidy=0 \| FileCheck %s`
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090 2014-03-29 18:18:08 +08:00			`; rdar://11935841`

			`define void @t1() nounwind ssp {`
			`entry:`
			`; CHECK-LABEL: t1:`
			`; CHECK-NOT: add x{{[0-9]+}}, sp`
			`; CHECK: stp x28, x27, [sp, #-16]!`
			`%v = alloca [288 x i32], align 4`
			`unreachable`
			`}`