2015-11-17 00:18:28 +08:00
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//===-- WebAssemblyRegStackify.cpp - Register Stackification --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file implements a register stacking pass.
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///
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/// This pass reorders instructions to put register uses and defs in an order
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/// such that they form single-use expression trees. Registers fitting this form
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/// are then marked as "stackified", meaning references to them are replaced by
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/// "push" and "pop" from the stack.
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///
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2015-12-08 11:43:03 +08:00
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/// This is primarily a code size optimization, since temporary values on the
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2015-11-17 00:18:28 +08:00
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/// expression don't need to be named.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssembly.h"
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2015-11-19 00:12:01 +08:00
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h" // for WebAssembly::ARGUMENT_*
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2015-11-30 06:32:02 +08:00
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#include "WebAssemblyMachineFunctionInfo.h"
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2016-01-20 00:59:23 +08:00
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#include "WebAssemblySubtarget.h"
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2015-11-26 00:55:01 +08:00
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#include "llvm/Analysis/AliasAnalysis.h"
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2015-12-25 08:31:02 +08:00
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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2015-11-17 00:18:28 +08:00
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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2016-01-28 09:22:44 +08:00
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2015-11-17 00:18:28 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-reg-stackify"
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namespace {
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class WebAssemblyRegStackify final : public MachineFunctionPass {
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const char *getPassName() const override {
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return "WebAssembly Register Stackify";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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2015-11-26 00:55:01 +08:00
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AU.addRequired<AAResultsWrapperPass>();
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2016-01-28 09:22:44 +08:00
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AU.addRequired<MachineDominatorTree>();
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2015-12-25 08:31:02 +08:00
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AU.addRequired<LiveIntervals>();
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2015-11-17 00:18:28 +08:00
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AU.addPreserved<MachineBlockFrequencyInfo>();
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2015-12-25 08:31:02 +08:00
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AU.addPreserved<SlotIndexes>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreservedID(LiveVariablesID);
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2016-01-28 09:22:44 +08:00
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AU.addPreserved<MachineDominatorTree>();
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2015-11-17 00:18:28 +08:00
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyRegStackify() : MachineFunctionPass(ID) {}
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};
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} // end anonymous namespace
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char WebAssemblyRegStackify::ID = 0;
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FunctionPass *llvm::createWebAssemblyRegStackify() {
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return new WebAssemblyRegStackify();
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}
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2015-11-20 10:19:12 +08:00
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// Decorate the given instruction with implicit operands that enforce the
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2015-12-25 08:31:02 +08:00
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// expression stack ordering constraints for an instruction which is on
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// the expression stack.
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static void ImposeStackOrdering(MachineInstr *MI) {
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2015-12-05 08:51:40 +08:00
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// Write the opaque EXPR_STACK register.
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if (!MI->definesRegister(WebAssembly::EXPR_STACK))
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MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
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/*isDef=*/true,
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/*isImp=*/true));
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// Also read the opaque EXPR_STACK register.
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2015-12-15 06:37:23 +08:00
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if (!MI->readsRegister(WebAssembly::EXPR_STACK))
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MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
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/*isDef=*/false,
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/*isImp=*/true));
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2015-11-20 10:19:12 +08:00
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}
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2015-12-25 08:31:02 +08:00
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// Test whether it's safe to move Def to just before Insert.
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2015-11-26 00:55:01 +08:00
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// TODO: Compute memory dependencies in a way that doesn't require always
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// walking the block.
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// TODO: Compute memory dependencies in a way that uses AliasAnalysis to be
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// more precise.
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static bool IsSafeToMove(const MachineInstr *Def, const MachineInstr *Insert,
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2016-01-28 09:22:44 +08:00
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AliasAnalysis &AA, const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI) {
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2015-12-04 07:07:03 +08:00
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assert(Def->getParent() == Insert->getParent());
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2015-11-26 00:55:01 +08:00
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bool SawStore = false, SawSideEffects = false;
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MachineBasicBlock::const_iterator D(Def), I(Insert);
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2015-12-25 08:31:02 +08:00
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// Check for register dependencies.
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for (const MachineOperand &MO : Def->operands()) {
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if (!MO.isReg() || MO.isUndef())
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continue;
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unsigned Reg = MO.getReg();
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// If the register is dead here and at Insert, ignore it.
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if (MO.isDead() && Insert->definesRegister(Reg) &&
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!Insert->readsRegister(Reg))
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continue;
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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2016-05-10 12:24:02 +08:00
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// Ignore ARGUMENTS; it's just used to keep the ARGUMENT_* instructions
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// from moving down, and we've already checked for that.
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if (Reg == WebAssembly::ARGUMENTS)
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continue;
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2015-12-25 08:31:02 +08:00
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// If the physical register is never modified, ignore it.
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if (!MRI.isPhysRegModified(Reg))
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continue;
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// Otherwise, it's a physical register with unknown liveness.
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return false;
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}
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// Ask LiveIntervals whether moving this virtual register use or def to
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2016-05-10 12:24:02 +08:00
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// Insert will change which value numbers are seen.
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2015-12-25 08:31:02 +08:00
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const LiveInterval &LI = LIS.getInterval(Reg);
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2016-01-20 00:59:23 +08:00
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VNInfo *DefVNI =
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2016-02-28 00:38:23 +08:00
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MO.isDef() ? LI.getVNInfoAt(LIS.getInstructionIndex(*Def).getRegSlot())
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: LI.getVNInfoBefore(LIS.getInstructionIndex(*Def));
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2015-12-25 08:31:02 +08:00
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assert(DefVNI && "Instruction input missing value number");
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2016-02-28 00:38:23 +08:00
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VNInfo *InsVNI = LI.getVNInfoBefore(LIS.getInstructionIndex(*Insert));
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2015-12-25 08:31:02 +08:00
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if (InsVNI && DefVNI != InsVNI)
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return false;
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}
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2016-02-17 05:44:19 +08:00
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SawStore = Def->isCall() || Def->mayStore();
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2015-12-25 08:31:02 +08:00
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// Check for memory dependencies and side effects.
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2015-11-26 00:55:01 +08:00
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for (--I; I != D; --I)
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2016-01-20 12:21:16 +08:00
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SawSideEffects |= !I->isSafeToMove(&AA, SawStore);
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2015-11-26 00:55:01 +08:00
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return !(SawStore && Def->mayLoad() && !Def->isInvariantLoad(&AA)) &&
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!(SawSideEffects && !Def->isSafeToMove(&AA, SawStore));
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}
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2016-01-28 09:22:44 +08:00
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/// Test whether OneUse, a use of Reg, dominates all of Reg's other uses.
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static bool OneUseDominatesOtherUses(unsigned Reg, const MachineOperand &OneUse,
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const MachineBasicBlock &MBB,
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const MachineRegisterInfo &MRI,
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2016-05-10 12:24:02 +08:00
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const MachineDominatorTree &MDT,
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LiveIntervals &LIS) {
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const LiveInterval &LI = LIS.getInterval(Reg);
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const MachineInstr *OneUseInst = OneUse.getParent();
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VNInfo *OneUseVNI = LI.getVNInfoBefore(LIS.getInstructionIndex(*OneUseInst));
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2016-01-28 09:22:44 +08:00
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for (const MachineOperand &Use : MRI.use_operands(Reg)) {
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if (&Use == &OneUse)
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continue;
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2016-05-10 12:24:02 +08:00
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2016-01-28 09:22:44 +08:00
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const MachineInstr *UseInst = Use.getParent();
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2016-05-10 12:24:02 +08:00
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VNInfo *UseVNI = LI.getVNInfoBefore(LIS.getInstructionIndex(*UseInst));
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if (UseVNI != OneUseVNI)
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continue;
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2016-01-28 09:22:44 +08:00
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const MachineInstr *OneUseInst = OneUse.getParent();
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if (UseInst->getOpcode() == TargetOpcode::PHI) {
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// Test that the PHI use, which happens on the CFG edge rather than
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// within the PHI's own block, is dominated by the one selected use.
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const MachineBasicBlock *Pred =
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UseInst->getOperand(&Use - &UseInst->getOperand(0) + 1).getMBB();
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if (!MDT.dominates(&MBB, Pred))
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return false;
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} else if (UseInst == OneUseInst) {
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// Another use in the same instruction. We need to ensure that the one
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// selected use happens "before" it.
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if (&OneUse > &Use)
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return false;
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} else {
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// Test that the use is dominated by the one selected use.
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if (!MDT.dominates(OneUseInst, UseInst))
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return false;
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}
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}
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return true;
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}
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/// Get the appropriate tee_local opcode for the given register class.
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static unsigned GetTeeLocalOpcode(const TargetRegisterClass *RC) {
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if (RC == &WebAssembly::I32RegClass)
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return WebAssembly::TEE_LOCAL_I32;
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if (RC == &WebAssembly::I64RegClass)
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return WebAssembly::TEE_LOCAL_I64;
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if (RC == &WebAssembly::F32RegClass)
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return WebAssembly::TEE_LOCAL_F32;
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if (RC == &WebAssembly::F64RegClass)
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return WebAssembly::TEE_LOCAL_F64;
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llvm_unreachable("Unexpected register class");
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}
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/// A single-use def in the same block with no intervening memory or register
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/// dependencies; move the def down and nest it with the current instruction.
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2016-05-10 12:24:02 +08:00
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static MachineInstr *MoveForSingleUse(unsigned Reg, MachineOperand& Op,
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MachineInstr *Def,
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2016-01-28 09:22:44 +08:00
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MachineBasicBlock &MBB,
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MachineInstr *Insert, LiveIntervals &LIS,
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2016-05-10 12:24:02 +08:00
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WebAssemblyFunctionInfo &MFI,
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MachineRegisterInfo &MRI) {
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2016-01-28 09:22:44 +08:00
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MBB.splice(Insert, &MBB, Def);
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2016-02-28 23:33:53 +08:00
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LIS.handleMove(*Def);
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2016-05-10 12:24:02 +08:00
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if (MRI.hasOneDef(Reg)) {
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MFI.stackifyVReg(Reg);
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} else {
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unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
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Def->getOperand(0).setReg(NewReg);
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Op.setReg(NewReg);
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// Tell LiveIntervals about the new register.
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LIS.createAndComputeVirtRegInterval(NewReg);
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// Tell LiveIntervals about the changes to the old register.
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LiveInterval &LI = LIS.getInterval(Reg);
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LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(*Def).getRegSlot());
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LIS.shrinkToUses(&LI);
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MFI.stackifyVReg(NewReg);
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}
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2016-01-28 09:22:44 +08:00
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ImposeStackOrdering(Def);
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return Def;
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}
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/// A trivially cloneable instruction; clone it and nest the new copy with the
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/// current instruction.
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static MachineInstr *
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RematerializeCheapDef(unsigned Reg, MachineOperand &Op, MachineInstr *Def,
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MachineBasicBlock &MBB, MachineInstr *Insert,
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LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI,
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MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII,
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const WebAssemblyRegisterInfo *TRI) {
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unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
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TII->reMaterialize(MBB, Insert, NewReg, 0, Def, *TRI);
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Op.setReg(NewReg);
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MachineInstr *Clone = &*std::prev(MachineBasicBlock::instr_iterator(Insert));
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2016-02-28 00:38:23 +08:00
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LIS.InsertMachineInstrInMaps(*Clone);
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2016-01-28 09:22:44 +08:00
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LIS.createAndComputeVirtRegInterval(NewReg);
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MFI.stackifyVReg(NewReg);
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ImposeStackOrdering(Clone);
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2016-05-10 12:24:02 +08:00
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// Shrink the interval.
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bool IsDead = MRI.use_empty(Reg);
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if (!IsDead) {
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LiveInterval &LI = LIS.getInterval(Reg);
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LIS.shrinkToUses(&LI);
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IsDead = !LI.liveAt(LIS.getInstructionIndex(*Def).getDeadSlot());
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}
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2016-01-28 09:22:44 +08:00
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// If that was the last use of the original, delete the original.
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2016-05-10 12:24:02 +08:00
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if (IsDead) {
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2016-02-28 00:38:23 +08:00
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SlotIndex Idx = LIS.getInstructionIndex(*Def).getRegSlot();
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2016-01-28 09:22:44 +08:00
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LIS.removePhysRegDefAt(WebAssembly::ARGUMENTS, Idx);
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LIS.removeInterval(Reg);
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2016-02-28 00:38:23 +08:00
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LIS.RemoveMachineInstrFromMaps(*Def);
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2016-01-28 09:22:44 +08:00
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Def->eraseFromParent();
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}
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2016-05-10 12:24:02 +08:00
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2016-01-28 09:22:44 +08:00
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return Clone;
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}
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/// A multiple-use def in the same block with no intervening memory or register
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/// dependencies; move the def down, nest it with the current instruction, and
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/// insert a tee_local to satisfy the rest of the uses. As an illustration,
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/// rewrite this:
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///
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/// Reg = INST ... // Def
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/// INST ..., Reg, ... // Insert
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/// INST ..., Reg, ...
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/// INST ..., Reg, ...
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///
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/// to this:
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///
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2016-02-16 23:17:21 +08:00
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/// DefReg = INST ... // Def (to become the new Insert)
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/// TeeReg, NewReg = TEE_LOCAL_... DefReg
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2016-01-28 09:22:44 +08:00
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/// INST ..., TeeReg, ... // Insert
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/// INST ..., NewReg, ...
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/// INST ..., NewReg, ...
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///
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2016-02-16 23:17:21 +08:00
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/// with DefReg and TeeReg stackified. This eliminates a get_local from the
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2016-01-28 09:22:44 +08:00
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/// resulting code.
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static MachineInstr *MoveAndTeeForMultiUse(
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unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB,
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MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI,
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MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII) {
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MBB.splice(Insert, &MBB, Def);
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2016-02-28 23:33:53 +08:00
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LIS.handleMove(*Def);
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2016-01-28 09:22:44 +08:00
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const auto *RegClass = MRI.getRegClass(Reg);
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unsigned NewReg = MRI.createVirtualRegister(RegClass);
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unsigned TeeReg = MRI.createVirtualRegister(RegClass);
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2016-02-16 23:17:21 +08:00
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unsigned DefReg = MRI.createVirtualRegister(RegClass);
|
2016-01-28 09:22:44 +08:00
|
|
|
MRI.replaceRegWith(Reg, NewReg);
|
|
|
|
MachineInstr *Tee = BuildMI(MBB, Insert, Insert->getDebugLoc(),
|
|
|
|
TII->get(GetTeeLocalOpcode(RegClass)), TeeReg)
|
|
|
|
.addReg(NewReg, RegState::Define)
|
2016-02-16 23:17:21 +08:00
|
|
|
.addReg(DefReg);
|
2016-01-28 09:22:44 +08:00
|
|
|
Op.setReg(TeeReg);
|
2016-02-16 23:17:21 +08:00
|
|
|
Def->getOperand(0).setReg(DefReg);
|
2016-02-28 00:38:23 +08:00
|
|
|
LIS.InsertMachineInstrInMaps(*Tee);
|
2016-02-16 23:17:21 +08:00
|
|
|
LIS.removeInterval(Reg);
|
2016-01-28 09:22:44 +08:00
|
|
|
LIS.createAndComputeVirtRegInterval(NewReg);
|
|
|
|
LIS.createAndComputeVirtRegInterval(TeeReg);
|
2016-02-16 23:17:21 +08:00
|
|
|
LIS.createAndComputeVirtRegInterval(DefReg);
|
|
|
|
MFI.stackifyVReg(DefReg);
|
2016-01-28 09:22:44 +08:00
|
|
|
MFI.stackifyVReg(TeeReg);
|
|
|
|
ImposeStackOrdering(Def);
|
|
|
|
ImposeStackOrdering(Tee);
|
|
|
|
return Def;
|
|
|
|
}
|
|
|
|
|
|
|
|
namespace {
|
|
|
|
/// A stack for walking the tree of instructions being built, visiting the
|
|
|
|
/// MachineOperands in DFS order.
|
|
|
|
class TreeWalkerState {
|
|
|
|
typedef MachineInstr::mop_iterator mop_iterator;
|
|
|
|
typedef std::reverse_iterator<mop_iterator> mop_reverse_iterator;
|
|
|
|
typedef iterator_range<mop_reverse_iterator> RangeTy;
|
|
|
|
SmallVector<RangeTy, 4> Worklist;
|
|
|
|
|
|
|
|
public:
|
|
|
|
explicit TreeWalkerState(MachineInstr *Insert) {
|
|
|
|
const iterator_range<mop_iterator> &Range = Insert->explicit_uses();
|
|
|
|
if (Range.begin() != Range.end())
|
|
|
|
Worklist.push_back(reverse(Range));
|
|
|
|
}
|
|
|
|
|
|
|
|
bool Done() const { return Worklist.empty(); }
|
|
|
|
|
|
|
|
MachineOperand &Pop() {
|
|
|
|
RangeTy &Range = Worklist.back();
|
|
|
|
MachineOperand &Op = *Range.begin();
|
|
|
|
Range = drop_begin(Range, 1);
|
|
|
|
if (Range.begin() == Range.end())
|
|
|
|
Worklist.pop_back();
|
|
|
|
assert((Worklist.empty() ||
|
|
|
|
Worklist.back().begin() != Worklist.back().end()) &&
|
|
|
|
"Empty ranges shouldn't remain in the worklist");
|
|
|
|
return Op;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Push Instr's operands onto the stack to be visited.
|
|
|
|
void PushOperands(MachineInstr *Instr) {
|
|
|
|
const iterator_range<mop_iterator> &Range(Instr->explicit_uses());
|
|
|
|
if (Range.begin() != Range.end())
|
|
|
|
Worklist.push_back(reverse(Range));
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Some of Instr's operands are on the top of the stack; remove them and
|
|
|
|
/// re-insert them starting from the beginning (because we've commuted them).
|
|
|
|
void ResetTopOperands(MachineInstr *Instr) {
|
|
|
|
assert(HasRemainingOperands(Instr) &&
|
|
|
|
"Reseting operands should only be done when the instruction has "
|
|
|
|
"an operand still on the stack");
|
|
|
|
Worklist.back() = reverse(Instr->explicit_uses());
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Test whether Instr has operands remaining to be visited at the top of
|
|
|
|
/// the stack.
|
|
|
|
bool HasRemainingOperands(const MachineInstr *Instr) const {
|
|
|
|
if (Worklist.empty())
|
|
|
|
return false;
|
|
|
|
const RangeTy &Range = Worklist.back();
|
|
|
|
return Range.begin() != Range.end() && Range.begin()->getParent() == Instr;
|
|
|
|
}
|
2016-01-28 11:59:09 +08:00
|
|
|
|
|
|
|
/// Test whether the given register is present on the stack, indicating an
|
|
|
|
/// operand in the tree that we haven't visited yet. Moving a definition of
|
|
|
|
/// Reg to a point in the tree after that would change its value.
|
|
|
|
bool IsOnStack(unsigned Reg) const {
|
|
|
|
for (const RangeTy &Range : Worklist)
|
|
|
|
for (const MachineOperand &MO : Range)
|
|
|
|
if (MO.isReg() && MO.getReg() == Reg)
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
2016-01-28 09:22:44 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
/// State to keep track of whether commuting is in flight or whether it's been
|
|
|
|
/// tried for the current instruction and didn't work.
|
|
|
|
class CommutingState {
|
|
|
|
/// There are effectively three states: the initial state where we haven't
|
|
|
|
/// started commuting anything and we don't know anything yet, the tenative
|
|
|
|
/// state where we've commuted the operands of the current instruction and are
|
|
|
|
/// revisting it, and the declined state where we've reverted the operands
|
|
|
|
/// back to their original order and will no longer commute it further.
|
|
|
|
bool TentativelyCommuting;
|
|
|
|
bool Declined;
|
|
|
|
|
|
|
|
/// During the tentative state, these hold the operand indices of the commuted
|
|
|
|
/// operands.
|
|
|
|
unsigned Operand0, Operand1;
|
|
|
|
|
|
|
|
public:
|
|
|
|
CommutingState() : TentativelyCommuting(false), Declined(false) {}
|
|
|
|
|
|
|
|
/// Stackification for an operand was not successful due to ordering
|
|
|
|
/// constraints. If possible, and if we haven't already tried it and declined
|
|
|
|
/// it, commute Insert's operands and prepare to revisit it.
|
|
|
|
void MaybeCommute(MachineInstr *Insert, TreeWalkerState &TreeWalker,
|
|
|
|
const WebAssemblyInstrInfo *TII) {
|
|
|
|
if (TentativelyCommuting) {
|
|
|
|
assert(!Declined &&
|
|
|
|
"Don't decline commuting until you've finished trying it");
|
|
|
|
// Commuting didn't help. Revert it.
|
|
|
|
TII->commuteInstruction(Insert, /*NewMI=*/false, Operand0, Operand1);
|
|
|
|
TentativelyCommuting = false;
|
|
|
|
Declined = true;
|
|
|
|
} else if (!Declined && TreeWalker.HasRemainingOperands(Insert)) {
|
|
|
|
Operand0 = TargetInstrInfo::CommuteAnyOperandIndex;
|
|
|
|
Operand1 = TargetInstrInfo::CommuteAnyOperandIndex;
|
|
|
|
if (TII->findCommutedOpIndices(Insert, Operand0, Operand1)) {
|
|
|
|
// Tentatively commute the operands and try again.
|
|
|
|
TII->commuteInstruction(Insert, /*NewMI=*/false, Operand0, Operand1);
|
|
|
|
TreeWalker.ResetTopOperands(Insert);
|
|
|
|
TentativelyCommuting = true;
|
|
|
|
Declined = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Stackification for some operand was successful. Reset to the default
|
|
|
|
/// state.
|
|
|
|
void Reset() {
|
|
|
|
TentativelyCommuting = false;
|
|
|
|
Declined = false;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
|
2015-11-17 00:18:28 +08:00
|
|
|
bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
|
|
|
|
DEBUG(dbgs() << "********** Register Stackifying **********\n"
|
|
|
|
"********** Function: "
|
|
|
|
<< MF.getName() << '\n');
|
|
|
|
|
|
|
|
bool Changed = false;
|
|
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
|
2016-01-20 00:59:23 +08:00
|
|
|
const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
|
|
|
|
const auto *TRI = MF.getSubtarget<WebAssemblySubtarget>().getRegisterInfo();
|
2015-11-26 00:55:01 +08:00
|
|
|
AliasAnalysis &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
|
2016-01-28 09:22:44 +08:00
|
|
|
MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
|
2015-12-25 08:31:02 +08:00
|
|
|
LiveIntervals &LIS = getAnalysis<LiveIntervals>();
|
2015-12-08 11:30:42 +08:00
|
|
|
|
2015-11-17 00:18:28 +08:00
|
|
|
// Walk the instructions from the bottom up. Currently we don't look past
|
|
|
|
// block boundaries, and the blocks aren't ordered so the block visitation
|
|
|
|
// order isn't significant, but we may want to change this in the future.
|
|
|
|
for (MachineBasicBlock &MBB : MF) {
|
2016-01-07 02:29:35 +08:00
|
|
|
// Don't use a range-based for loop, because we modify the list as we're
|
|
|
|
// iterating over it and the end iterator may change.
|
|
|
|
for (auto MII = MBB.rbegin(); MII != MBB.rend(); ++MII) {
|
|
|
|
MachineInstr *Insert = &*MII;
|
2015-11-17 00:18:28 +08:00
|
|
|
// Don't nest anything inside a phi.
|
|
|
|
if (Insert->getOpcode() == TargetOpcode::PHI)
|
|
|
|
break;
|
|
|
|
|
2015-11-26 00:55:01 +08:00
|
|
|
// Don't nest anything inside an inline asm, because we don't have
|
|
|
|
// constraints for $push inputs.
|
|
|
|
if (Insert->getOpcode() == TargetOpcode::INLINEASM)
|
2016-02-23 01:45:20 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
// Ignore debugging intrinsics.
|
|
|
|
if (Insert->getOpcode() == TargetOpcode::DBG_VALUE)
|
|
|
|
continue;
|
2015-11-26 00:55:01 +08:00
|
|
|
|
2015-11-17 00:18:28 +08:00
|
|
|
// Iterate through the inputs in reverse order, since we'll be pulling
|
2015-12-03 02:08:49 +08:00
|
|
|
// operands off the stack in LIFO order.
|
2016-01-28 09:22:44 +08:00
|
|
|
CommutingState Commuting;
|
|
|
|
TreeWalkerState TreeWalker(Insert);
|
|
|
|
while (!TreeWalker.Done()) {
|
|
|
|
MachineOperand &Op = TreeWalker.Pop();
|
|
|
|
|
2015-11-17 00:18:28 +08:00
|
|
|
// We're only interested in explicit virtual register operands.
|
2016-01-28 09:22:44 +08:00
|
|
|
if (!Op.isReg())
|
2015-11-17 00:18:28 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
unsigned Reg = Op.getReg();
|
2016-01-28 09:22:44 +08:00
|
|
|
assert(Op.isUse() && "explicit_uses() should only iterate over uses");
|
|
|
|
assert(!Op.isImplicit() &&
|
|
|
|
"explicit_uses() should only iterate over explicit operands");
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
|
|
continue;
|
2015-11-17 00:18:28 +08:00
|
|
|
|
2016-01-28 09:22:44 +08:00
|
|
|
// Identify the definition for this register at this point. Most
|
|
|
|
// registers are in SSA form here so we try a quick MRI query first.
|
2015-12-25 08:31:02 +08:00
|
|
|
MachineInstr *Def = MRI.getUniqueVRegDef(Reg);
|
2016-01-28 09:22:44 +08:00
|
|
|
if (!Def) {
|
|
|
|
// MRI doesn't know what the Def is. Try asking LIS.
|
|
|
|
const VNInfo *ValNo = LIS.getInterval(Reg).getVNInfoBefore(
|
2016-02-28 00:38:23 +08:00
|
|
|
LIS.getInstructionIndex(*Insert));
|
2016-01-28 09:22:44 +08:00
|
|
|
if (!ValNo)
|
|
|
|
continue;
|
|
|
|
Def = LIS.getInstructionFromIndex(ValNo->def);
|
|
|
|
if (!Def)
|
|
|
|
continue;
|
|
|
|
}
|
2015-11-17 00:18:28 +08:00
|
|
|
|
2015-11-26 00:55:01 +08:00
|
|
|
// Don't nest an INLINE_ASM def into anything, because we don't have
|
|
|
|
// constraints for $pop outputs.
|
|
|
|
if (Def->getOpcode() == TargetOpcode::INLINEASM)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Don't nest PHIs inside of anything.
|
|
|
|
if (Def->getOpcode() == TargetOpcode::PHI)
|
|
|
|
continue;
|
|
|
|
|
2015-11-19 00:12:01 +08:00
|
|
|
// Argument instructions represent live-in registers and not real
|
|
|
|
// instructions.
|
|
|
|
if (Def->getOpcode() == WebAssembly::ARGUMENT_I32 ||
|
|
|
|
Def->getOpcode() == WebAssembly::ARGUMENT_I64 ||
|
|
|
|
Def->getOpcode() == WebAssembly::ARGUMENT_F32 ||
|
|
|
|
Def->getOpcode() == WebAssembly::ARGUMENT_F64)
|
|
|
|
continue;
|
|
|
|
|
2016-01-28 09:22:44 +08:00
|
|
|
// Decide which strategy to take. Prefer to move a single-use value
|
|
|
|
// over cloning it, and prefer cloning over introducing a tee_local.
|
|
|
|
// For moving, we require the def to be in the same block as the use;
|
|
|
|
// this makes things simpler (LiveIntervals' handleMove function only
|
|
|
|
// supports intra-block moves) and it's MachineSink's job to catch all
|
|
|
|
// the sinking opportunities anyway.
|
|
|
|
bool SameBlock = Def->getParent() == &MBB;
|
2016-01-28 11:59:09 +08:00
|
|
|
bool CanMove = SameBlock && IsSafeToMove(Def, Insert, AA, LIS, MRI) &&
|
|
|
|
!TreeWalker.IsOnStack(Reg);
|
2016-01-28 09:22:44 +08:00
|
|
|
if (CanMove && MRI.hasOneUse(Reg)) {
|
2016-05-10 12:24:02 +08:00
|
|
|
Insert = MoveForSingleUse(Reg, Op, Def, MBB, Insert, LIS, MFI, MRI);
|
2016-01-20 00:59:23 +08:00
|
|
|
} else if (Def->isAsCheapAsAMove() &&
|
|
|
|
TII->isTriviallyReMaterializable(Def, &AA)) {
|
2016-01-28 09:22:44 +08:00
|
|
|
Insert = RematerializeCheapDef(Reg, Op, Def, MBB, Insert, LIS, MFI,
|
|
|
|
MRI, TII, TRI);
|
|
|
|
} else if (CanMove &&
|
2016-05-10 12:24:02 +08:00
|
|
|
OneUseDominatesOtherUses(Reg, Op, MBB, MRI, MDT, LIS)) {
|
2016-01-28 09:22:44 +08:00
|
|
|
Insert = MoveAndTeeForMultiUse(Reg, Op, Def, MBB, Insert, LIS, MFI,
|
|
|
|
MRI, TII);
|
|
|
|
} else {
|
|
|
|
// We failed to stackify the operand. If the problem was ordering
|
|
|
|
// constraints, Commuting may be able to help.
|
|
|
|
if (!CanMove && SameBlock)
|
|
|
|
Commuting.MaybeCommute(Insert, TreeWalker, TII);
|
|
|
|
// Proceed to the next operand.
|
|
|
|
continue;
|
2016-01-20 00:59:23 +08:00
|
|
|
}
|
2016-01-28 09:22:44 +08:00
|
|
|
|
|
|
|
// We stackified an operand. Add the defining instruction's operands to
|
|
|
|
// the worklist stack now to continue to build an ever deeper tree.
|
|
|
|
Commuting.Reset();
|
|
|
|
TreeWalker.PushOperands(Insert);
|
2015-11-17 00:18:28 +08:00
|
|
|
}
|
2016-01-28 09:22:44 +08:00
|
|
|
|
|
|
|
// If we stackified any operands, skip over the tree to start looking for
|
|
|
|
// the next instruction we can build a tree on.
|
|
|
|
if (Insert != &*MII) {
|
2016-01-07 02:29:35 +08:00
|
|
|
ImposeStackOrdering(&*MII);
|
2016-01-28 09:22:44 +08:00
|
|
|
MII = std::prev(
|
2016-03-14 19:04:15 +08:00
|
|
|
llvm::make_reverse_iterator(MachineBasicBlock::iterator(Insert)));
|
2016-01-28 09:22:44 +08:00
|
|
|
Changed = true;
|
|
|
|
}
|
2015-11-17 00:18:28 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-01-28 09:22:44 +08:00
|
|
|
// If we used EXPR_STACK anywhere, add it to the live-in sets everywhere so
|
|
|
|
// that it never looks like a use-before-def.
|
2015-11-20 10:19:12 +08:00
|
|
|
if (Changed) {
|
|
|
|
MF.getRegInfo().addLiveIn(WebAssembly::EXPR_STACK);
|
|
|
|
for (MachineBasicBlock &MBB : MF)
|
|
|
|
MBB.addLiveIn(WebAssembly::EXPR_STACK);
|
|
|
|
}
|
|
|
|
|
2015-11-20 10:33:24 +08:00
|
|
|
#ifndef NDEBUG
|
2016-01-20 00:59:23 +08:00
|
|
|
// Verify that pushes and pops are performed in LIFO order.
|
2015-11-20 10:33:24 +08:00
|
|
|
SmallVector<unsigned, 0> Stack;
|
|
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
|
|
for (MachineInstr &MI : MBB) {
|
2016-05-10 12:24:02 +08:00
|
|
|
if (MI.isDebugValue())
|
|
|
|
continue;
|
2015-11-20 10:33:24 +08:00
|
|
|
for (MachineOperand &MO : reverse(MI.explicit_operands())) {
|
2015-11-30 06:32:02 +08:00
|
|
|
if (!MO.isReg())
|
|
|
|
continue;
|
2016-01-28 09:22:44 +08:00
|
|
|
unsigned Reg = MO.getReg();
|
2015-11-20 10:33:24 +08:00
|
|
|
|
2016-01-28 09:22:44 +08:00
|
|
|
if (MFI.isVRegStackified(Reg)) {
|
2015-11-20 10:33:24 +08:00
|
|
|
if (MO.isDef())
|
2016-01-28 09:22:44 +08:00
|
|
|
Stack.push_back(Reg);
|
2015-11-20 10:33:24 +08:00
|
|
|
else
|
2016-01-28 09:22:44 +08:00
|
|
|
assert(Stack.pop_back_val() == Reg &&
|
|
|
|
"Register stack pop should be paired with a push");
|
2015-11-20 10:33:24 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// TODO: Generalize this code to support keeping values on the stack across
|
|
|
|
// basic block boundaries.
|
2016-01-28 09:22:44 +08:00
|
|
|
assert(Stack.empty() &&
|
|
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"Register stack pushes and pops should be balanced");
|
2015-11-20 10:33:24 +08:00
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}
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#endif
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|
|
2015-11-17 00:18:28 +08:00
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|
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return Changed;
|
|
|
|
}
|