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llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir

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GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR. These are the operations that are trivially identical. Division is omitted for now because you need to use the correct sign/zero extension. llvm-svn: 277775
2016-08-05 05:39:49 +08:00
# RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-apple-ios"
define void @test_scalar_or_small() {
entry:
ret void
}
...
---
name: test_scalar_or_small
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
GlobalISel: forbid physical registers on generic MIs. We're intending to move to a world where the type of a register is determined by its (unique) def. This is incompatible with physregs, which are untyped. It also means the other passes don't have to worry quite so much about register-class compatibility and inserting COPYs appropriately. llvm-svn: 280132
2016-08-31 02:52:46 +08:00
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR. These are the operations that are trivially identical. Division is omitted for now because you need to use the correct sign/zero extension. llvm-svn: 277775
2016-08-05 05:39:49 +08:00
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
; CHECK-LABEL: name: test_scalar_or_small
GlobalISel: move type information to MachineRegisterInfo. We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
2016-09-09 19:46:34 +08:00
; CHECK: %4(s8) = G_OR %2, %3
GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR. These are the operations that are trivially identical. Division is omitted for now because you need to use the correct sign/zero extension. llvm-svn: 277775
2016-08-05 05:39:49 +08:00
GlobalISel: move type information to MachineRegisterInfo. We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
2016-09-09 19:46:34 +08:00
%0(s64) = G_TYPE %x0
%1(s64) = G_TYPE %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_OR %2, %3
%5(s64) = G_ANYEXT %2
GlobalISel: forbid physical registers on generic MIs. We're intending to move to a world where the type of a register is determined by its (unique) def. This is incompatible with physregs, which are untyped. It also means the other passes don't have to worry quite so much about register-class compatibility and inserting COPYs appropriately. llvm-svn: 280132
2016-08-31 02:52:46 +08:00
%x0 = COPY %5
GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR. These are the operations that are trivially identical. Division is omitted for now because you need to use the correct sign/zero extension. llvm-svn: 277775
2016-08-05 05:39:49 +08:00
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