maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/X86/zext-inreg-1.ll

19 lines
521 B
LLVM
Raw Normal View History

X86: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309774
2017-08-02 08:28:10 +08:00
; RUN: llc < %s -mtriple=i686-- | not grep and
Reapply r54147 with a constraint to only use the 8-bit subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. llvm-svn: 54223
2008-07-31 02:09:17 +08:00
; These tests differ from the ones in zext-inreg-0.ll in that
; on x86-64 they do require and instructions.
; These should use movzbl instead of 'and 255'.
; This related to not having ZERO_EXTEND_REG node.
Add an extra example that shouldn't get an and instruction. llvm-svn: 54443
2008-08-07 10:23:06 +08:00
define i64 @l(i64 %d) nounwind {
%e = add i64 %d, 1
%retval = and i64 %e, 1099511627775
ret i64 %retval
}
define i64 @m(i64 %d) nounwind {
Reapply r54147 with a constraint to only use the 8-bit subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. llvm-svn: 54223
2008-07-31 02:09:17 +08:00
%e = add i64 %d, 1
%retval = and i64 %e, 281474976710655
ret i64 %retval
}