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llvm-project/llvm/test/CodeGen/X86/mfence.ll

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[x86-64] allow mfence even with -mno-sse (PR23203) As shown in: https://llvm.org/bugs/show_bug.cgi?id=23203 ...we currently die because lowering believes that mfence is allowed without SSE2 on x86-64, but the instruction def doesn't know that. I don't know if allowing mfence without SSE is right, but if not, at least now it's consistently wrong. :) Differential Revision: http://reviews.llvm.org/D17219 llvm-svn: 260828
2016-02-14 01:26:29 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64
; It doesn't matter if an x86-64 target has specified "no-sse2"; we still can use mfence.
llvm.memory.barrier, and impl for x86 and alpha llvm-svn: 47204
2008-02-16 09:24:58 +08:00
define void @test() {
[x86-64] allow mfence even with -mno-sse (PR23203) As shown in: https://llvm.org/bugs/show_bug.cgi?id=23203 ...we currently die because lowering believes that mfence is allowed without SSE2 on x86-64, but the instruction def doesn't know that. I don't know if allowing mfence without SSE is right, but if not, at least now it's consistently wrong. :) Differential Revision: http://reviews.llvm.org/D17219 llvm-svn: 260828
2016-02-14 01:26:29 +08:00
; X32-LABEL: test:
; X32: # BB#0:
; X32-NEXT: mfence
; X32-NEXT: retl
;
; X64-LABEL: test:
; X64: # BB#0:
; X64-NEXT: mfence
; X64-NEXT: retq
Last batch of test conversions to new atomic instructions. llvm-svn: 140585
2011-09-27 08:17:29 +08:00
fence seq_cst
ret void
llvm.memory.barrier, and impl for x86 and alpha llvm-svn: 47204
2008-02-16 09:24:58 +08:00
}
fix test to use FileCheck llvm-svn: 260751
2016-02-13 06:07:54 +08:00
[x86-64] allow mfence even with -mno-sse (PR23203) As shown in: https://llvm.org/bugs/show_bug.cgi?id=23203 ...we currently die because lowering believes that mfence is allowed without SSE2 on x86-64, but the instruction def doesn't know that. I don't know if allowing mfence without SSE is right, but if not, at least now it's consistently wrong. :) Differential Revision: http://reviews.llvm.org/D17219 llvm-svn: 260828
2016-02-14 01:26:29 +08:00
define i32 @fence(i32* %ptr) {
; X32-LABEL: fence:
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: mfence
; X32-NEXT: movl (%eax), %eax
; X32-NEXT: retl
;
; X64-LABEL: fence:
; X64: # BB#0:
; X64-NEXT: mfence
; X64-NEXT: movl (%rdi), %eax
; X64-NEXT: retq
%atomic = atomicrmw add i32* %ptr, i32 0 seq_cst
ret i32 %atomic
}