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llvm-project/llvm/test/CodeGen/X86/legalize-shl-vec.ll

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[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=X64
Reapply fixed r241790: Fix shift legalization and lowering for big constants. Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
2015-07-09 22:58:04 +08:00
define <2 x i256> @test_shl(<2 x i256> %In) {
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-LABEL: test_shl:
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl $0, 60(%eax)
; X32-NEXT: movl $0, 56(%eax)
; X32-NEXT: movl $0, 52(%eax)
; X32-NEXT: movl $0, 48(%eax)
; X32-NEXT: movl $0, 44(%eax)
; X32-NEXT: movl $0, 40(%eax)
; X32-NEXT: movl $0, 36(%eax)
; X32-NEXT: movl $0, 32(%eax)
; X32-NEXT: movl $0, 28(%eax)
; X32-NEXT: movl $0, 24(%eax)
; X32-NEXT: movl $0, 20(%eax)
; X32-NEXT: movl $0, 16(%eax)
; X32-NEXT: movl $0, 12(%eax)
; X32-NEXT: movl $0, 8(%eax)
; X32-NEXT: movl $0, 4(%eax)
; X32-NEXT: movl $0, (%eax)
; X32-NEXT: retl $4
;
; X64-LABEL: test_shl:
; X64: # BB#0:
[X86][DAG] Switch X86 Target to post-legalized store merge Move store merge to happen after intrinsic lowering to allow lowered stores to be merged. Some regressions due in MergeConsecutiveStores to missing insert_subvector that are addressed in follow up patch. Reviewers: craig.topper, efriedma, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34559 llvm-svn: 310710
2017-08-11 21:21:35 +08:00
; X64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, 48(%rdi)
; X64-NEXT: movaps %xmm0, 32(%rdi)
; X64-NEXT: movaps %xmm0, 16(%rdi)
; X64-NEXT: movaps %xmm0, (%rdi)
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: retq
Reapply fixed r241790: Fix shift legalization and lowering for big constants. Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
2015-07-09 22:58:04 +08:00
%Amt = insertelement <2 x i256> undef, i256 -1, i32 0
%Out = shl <2 x i256> %In, %Amt
ret <2 x i256> %Out
}
define <2 x i256> @test_srl(<2 x i256> %In) {
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-LABEL: test_srl:
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl $0, 60(%eax)
; X32-NEXT: movl $0, 56(%eax)
; X32-NEXT: movl $0, 52(%eax)
; X32-NEXT: movl $0, 48(%eax)
; X32-NEXT: movl $0, 44(%eax)
; X32-NEXT: movl $0, 40(%eax)
; X32-NEXT: movl $0, 36(%eax)
; X32-NEXT: movl $0, 32(%eax)
; X32-NEXT: movl $0, 28(%eax)
; X32-NEXT: movl $0, 24(%eax)
; X32-NEXT: movl $0, 20(%eax)
; X32-NEXT: movl $0, 16(%eax)
; X32-NEXT: movl $0, 12(%eax)
; X32-NEXT: movl $0, 8(%eax)
; X32-NEXT: movl $0, 4(%eax)
; X32-NEXT: movl $0, (%eax)
; X32-NEXT: retl $4
;
; X64-LABEL: test_srl:
; X64: # BB#0:
[X86][DAG] Switch X86 Target to post-legalized store merge Move store merge to happen after intrinsic lowering to allow lowered stores to be merged. Some regressions due in MergeConsecutiveStores to missing insert_subvector that are addressed in follow up patch. Reviewers: craig.topper, efriedma, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34559 llvm-svn: 310710
2017-08-11 21:21:35 +08:00
; X64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, 48(%rdi)
; X64-NEXT: movaps %xmm0, 32(%rdi)
; X64-NEXT: movaps %xmm0, 16(%rdi)
; X64-NEXT: movaps %xmm0, (%rdi)
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: retq
Reapply fixed r241790: Fix shift legalization and lowering for big constants. Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
2015-07-09 22:58:04 +08:00
%Amt = insertelement <2 x i256> undef, i256 -1, i32 0
%Out = lshr <2 x i256> %In, %Amt
ret <2 x i256> %Out
}
define <2 x i256> @test_sra(<2 x i256> %In) {
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-LABEL: test_sra:
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %ecx, 60(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %ecx, 56(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %ecx, 52(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %ecx, 48(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %ecx, 44(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %ecx, 40(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %ecx, 36(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %ecx, 32(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: sarl $31, %ecx
; X32-NEXT: movl %ecx, 28(%eax)
; X32-NEXT: movl %ecx, 24(%eax)
; X32-NEXT: movl %ecx, 20(%eax)
; X32-NEXT: movl %ecx, 16(%eax)
; X32-NEXT: movl %ecx, 12(%eax)
; X32-NEXT: movl %ecx, 8(%eax)
; X32-NEXT: movl %ecx, 4(%eax)
; X32-NEXT: movl %ecx, (%eax)
; X32-NEXT: retl $4
;
; X64-LABEL: test_sra:
; X64: # BB#0:
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; X64-NEXT: sarq $63, %r8
; X64-NEXT: movq %rdx, 56(%rdi)
; X64-NEXT: movq %rcx, 48(%rdi)
; X64-NEXT: movq %rax, 40(%rdi)
; X64-NEXT: movq %r9, 32(%rdi)
; X64-NEXT: movq %r8, 24(%rdi)
; X64-NEXT: movq %r8, 16(%rdi)
; X64-NEXT: movq %r8, 8(%rdi)
; X64-NEXT: movq %r8, (%rdi)
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: retq
Reapply fixed r241790: Fix shift legalization and lowering for big constants. Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
2015-07-09 22:58:04 +08:00
%Amt = insertelement <2 x i256> undef, i256 -1, i32 0
%Out = ashr <2 x i256> %In, %Amt
ret <2 x i256> %Out
}