2017-09-29 17:49:35 +08:00
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; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tahiti | FileCheck --check-prefix=PAL --enable-var-scope %s
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2017-09-29 17:48:12 +08:00
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2018-02-06 21:39:38 +08:00
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; PAL-NOT: .AMDGPU.config
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; PAL-LABEL: {{^}}simple:
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2017-09-29 17:48:12 +08:00
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define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
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entry:
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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2017-09-29 17:49:35 +08:00
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; Check code sequence for amdpal use of scratch for alloca. This is the case
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; where the high half of the address comes from s_getpc.
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; PAL-LABEL: {{^}}scratch:
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; PAL: s_getpc_b64 s{{\[}}[[GITPTR:[0-9]+]]:
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; PAL: s_mov_b32 s[[GITPTR]], s0
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; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
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; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
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2018-02-03 00:07:16 +08:00
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define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) {
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2017-09-29 17:49:35 +08:00
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entry:
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2018-02-03 00:07:16 +08:00
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%v = alloca [2 x i32], addrspace(5)
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%vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
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store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
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%e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
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%x = load i32, i32 addrspace(5)* %e
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store i32 %x, i32 addrspace(5)* %out
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2017-09-29 17:49:35 +08:00
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ret void
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}
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; Check code sequence for amdpal use of scratch for alloca. This is the case
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; where the amdgpu-git-ptr-high function attribute gives the high half of the
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; address to use.
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; Looks like you can't do arithmetic on a filecheck variable, so we can't test
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; that the s_movk_i32 is into a reg that is one more than the following
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; s_mov_b32.
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; PAL-LABEL: {{^}}scratch2:
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; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
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; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
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; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
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; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
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2018-02-03 00:07:16 +08:00
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define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) #0 {
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2017-09-29 17:49:35 +08:00
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entry:
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2018-02-03 00:07:16 +08:00
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%v = alloca [2 x i32], addrspace(5)
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%vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
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store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
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%e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
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%x = load i32, i32 addrspace(5)* %e
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store i32 %x, i32 addrspace(5)* %out
|
2017-09-29 17:49:35 +08:00
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ret void
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}
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[AMDGPU] For OS type AMDPAL, fixed scratch on compute shader
Summary:
For OS type AMDPAL, the scratch descriptor is loaded from offset 0 of
the GIT, whose 32 bit pointer is in s0 (s8 for gfx9 merged shaders).
This commit fixes that to use offset 0x10 instead of offset 0 for a
compute shader, per the PAL ABI spec.
V2: Ensure s0 (s8 for gfx9 merged shader) is marked live-in when loading
scratch descriptor from GIT.
Reviewers: kzhuravl, nhaehnle, timcorringham
Subscribers: kzhuravl, wdng, yaxunl, t-tye, llvm-commits, dstuttard, nhaehnle, arsenm
Differential Revision: https://reviews.llvm.org/D44468
Change-Id: I93dffa647758e37f613bb5e0dfca840d82e6d26f
llvm-svn: 329690
2018-04-10 19:25:15 +08:00
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; Check code sequence for amdpal use of scratch for alloca in a compute shader.
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; The scratch descriptor is loaded from offset 0x10 of the GIT, rather than offset
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; 0 in a graphics shader.
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; PAL-LABEL: {{^}}scratch2_cs:
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; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
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; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
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; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:{{[0-9]+\]}}, 0x10
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; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
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define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 {
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|
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|
entry:
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|
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|
%v = alloca [3 x i32], addrspace(5)
|
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|
%v0 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 0
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%v1 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 1
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|
store i32 %extra, i32 addrspace(5)* %v0
|
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|
%v1a = bitcast i32 addrspace(5)* %v1 to [2 x i32] addrspace(5)*
|
|
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|
%vv = bitcast [2 x i32] addrspace(5)* %v1a to <2 x i32> addrspace(5)*
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|
|
|
store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
|
|
|
|
%e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v1a, i32 0, i32 %idx
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|
|
|
%x = load i32, i32 addrspace(5)* %e
|
|
|
|
%xf = bitcast i32 %x to float
|
|
|
|
call void @llvm.amdgcn.buffer.store.f32(float %xf, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
2017-09-29 17:49:35 +08:00
|
|
|
attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" }
|
2017-11-15 07:05:36 +08:00
|
|
|
|
[AMDGPU] For OS type AMDPAL, fixed scratch on compute shader
Summary:
For OS type AMDPAL, the scratch descriptor is loaded from offset 0 of
the GIT, whose 32 bit pointer is in s0 (s8 for gfx9 merged shaders).
This commit fixes that to use offset 0x10 instead of offset 0 for a
compute shader, per the PAL ABI spec.
V2: Ensure s0 (s8 for gfx9 merged shader) is marked live-in when loading
scratch descriptor from GIT.
Reviewers: kzhuravl, nhaehnle, timcorringham
Subscribers: kzhuravl, wdng, yaxunl, t-tye, llvm-commits, dstuttard, nhaehnle, arsenm
Differential Revision: https://reviews.llvm.org/D44468
Change-Id: I93dffa647758e37f613bb5e0dfca840d82e6d26f
llvm-svn: 329690
2018-04-10 19:25:15 +08:00
|
|
|
declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1)
|
|
|
|
|
|
|
|
|
2017-11-15 07:05:36 +08:00
|
|
|
; Check we have CS_NUM_USED_VGPRS in PAL metadata.
|
|
|
|
; PAL: .amd_amdgpu_pal_metadata {{.*}},0x10000027,
|