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[TableGen] Remove spurious GISEL prefix from test. Differential Revision: https://reviews.llvm.org/D90480
2020-10-31 01:31:29 +08:00
// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-NOOPT %s
// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=true -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-OPT %s
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 22:39:21 +08:00
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
TableGen/GlobalISel: Allow inst matcher to check multiple opcodes This is to initially handleg immAllOnesV, which should match G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC. In the future, it could be used for other patterns cases that map to multiple G_* instructions, such as G_ADD and G_PTR_ADD.
2020-08-03 02:52:20 +08:00
// GISEL-OPT: GIM_SwitchOpcode
// GISEL-OPT-NEXT: /*TargetOpcode::G_SHL*/
// GISEL-OPT-NEXT: /*TargetOpcode::G_LSHR*/
// GISEL-OPT-NEXT: // Label
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 22:39:21 +08:00
TableGen/GlobalISel: Allow inst matcher to check multiple opcodes This is to initially handleg immAllOnesV, which should match G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC. In the future, it could be used for other patterns cases that map to multiple G_* instructions, such as G_ADD and G_PTR_ADD.
2020-08-03 02:52:20 +08:00
// GISEL-OPT: GIM_Try,
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 22:39:21 +08:00
// GISEL-OPT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
TableGen/GlobalISel: Allow inst matcher to check multiple opcodes This is to initially handleg immAllOnesV, which should match G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC. In the future, it could be used for other patterns cases that map to multiple G_* instructions, such as G_ADD and G_PTR_ADD.
2020-08-03 02:52:20 +08:00
// GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC,
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 22:39:21 +08:00
// GISEL-OPT: GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
TableGen/GlobalISel: Allow inst matcher to check multiple opcodes This is to initially handleg immAllOnesV, which should match G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC. In the future, it could be used for other patterns cases that map to multiple G_* instructions, such as G_ADD and G_PTR_ADD.
2020-08-03 02:52:20 +08:00
// GISEL-OPT: GIM_Try,
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 22:39:21 +08:00
// GISEL-OPT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
TableGen/GlobalISel: Allow inst matcher to check multiple opcodes This is to initially handleg immAllOnesV, which should match G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC. In the future, it could be used for other patterns cases that map to multiple G_* instructions, such as G_ADD and G_PTR_ADD.
2020-08-03 02:52:20 +08:00
// GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC,
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 22:39:21 +08:00
// GISEL-OPT: GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
// GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LSHR,
// GISEL-NOOPT: // MIs[0] Operand 2
// GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
// GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
TableGen/GlobalISel: Allow inst matcher to check multiple opcodes This is to initially handleg immAllOnesV, which should match G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC. In the future, it could be used for other patterns cases that map to multiple G_* instructions, such as G_ADD and G_PTR_ADD.
2020-08-03 02:52:20 +08:00
// GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC,
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 22:39:21 +08:00
// GISEL-NOOPT-NEXT: GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
// GISEL-NOOPT-NEXT: // MIs[1] Operand 0
// GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
// GISEL-NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
// GISEL-NOOPT-NEXT: // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, immAllOnesV:{ *:[v4i16] }) => (VFOOONES:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0)
def VFOOONES : I<(outs VecReg128:$dst), (ins VecReg128:$src0),
[(set v4i32:$dst, (srl v4i32:$src0, (v4i16 immAllOnesV)))]
>;
// GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SHL,
// GISEL-NOOPT: // MIs[0] Operand 2
// GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
// GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
TableGen/GlobalISel: Allow inst matcher to check multiple opcodes This is to initially handleg immAllOnesV, which should match G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC. In the future, it could be used for other patterns cases that map to multiple G_* instructions, such as G_ADD and G_PTR_ADD.
2020-08-03 02:52:20 +08:00
// GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC,
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 22:39:21 +08:00
// GISEL-NOOPT-NEXT: GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
// GISEL-NOOPT-NEXT: // MIs[1] Operand 0
// GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
// GISEL-NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
// GISEL-NOOPT-NEXT: // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, immAllZerosV:{ *:[v4i16] }) => (VFOOZERO:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0)
def VFOOZERO : I<(outs VecReg128:$dst), (ins VecReg128:$src0),
[(set v4i32:$dst, (shl v4i32:$src0, (v4i16 immAllZerosV)))]
>;